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_CUBIC
COMMUNICATIONS
SWAIII DIVISIDN
1
I
1
10 UIOI
+.v
+,v
RI05
COUNTER INPUT
AMPLIFIER
and RIIO forming the bias network
and Rlll,
bypassed by CI09,
the emitter
circuit.
The output of Ql03, now
gain~levelled
and amplified, is applied to
the base of Ql04 through
CIOS.
Since the desired
output of this
stage is
a square
wave
suitable
for driving the
counter
prescaler, and linearity
is no
longer of import-
ance,
RIl?
suffices to
provide
bias for
QI04.
The collector is direct-
ly coupled to
the input
of the prescaler.
Ul02, a
divide-by-
ten
counter,
reduces
the
frequency
of
the
incoming
signal
from
the
input range
of ap-
proximately 10.S to 39
MHz (9 MHz above the transceiver operating frequency) to 1.OS to 3.9 MHz for
the input
of the counter proper.
It is cleared
at the end
of each count
cycle by the
negative-going pulse on the
clr line.
This line provides the
necessary gate function to drive the counter proper.
The counter chain
is conventional,
with two exceptions; the output of
the prescaler
is still too high for reliable operation of the CMOS devices,
particularly complex devices such as counters, on a 5 volt SUPplYi hence, in
this decade,
a low-power Schottky device is used.
This counter,
the least
significant figure decade (100 Hz on the display),
counts using the conven-
tional BCD code,
and its
four output lines
drive UI05, a combined storage
latch, decoder, and seven-segment display driver.
When the end of the count
cycle is reached, the xfr line is brought momentarily low causing the latch-
es in Ul05 to accept the data being fed to it by UI04, and to store it until
updated
at the end of the
next counting cycle.
This data is then decoded,
and the proper segments of thedisplay, CR201, are activated, displaying the
count.
CR201 is a common anode type of display, so grounding the input pins
for the appropriate segments
will cause them
to
ligh~.
Current is limited
to the correct value (15 mA) by internal circuitry of UI05.
Rl19 is used to
provide a path to ground for the decimal point
of CR201,
and to
limit its
current, so that it is lighted at all times the radio is on.
The second
somewhat unusual
feature of the counter is that the output
of the LSD decade
is not
taken from the
counter
"carry" output,
for the
pulse presented here is much too narrow for the following, CMOS decade.
In-
stead, output is taken from the QD terminal, through current
limiting res-
istor R120,
and applied to the base of QlO?
The collector,
with pull up
resistor Rl21,
is connected to the input of the next
decade counter, ul06
0
The pulse
thus obtained is much wider
than that presented at
the "carry"
output, and is inverted to the correct polarity.
The subsequent decades of the counter are all of the CMOS family--UI06,
UlOS, UlIO and Ul12.
Each has a "carry" output
which is used to drive dir-
ectly
the "up count"
input of the
subsequent
decade.
Each has
four BCD
codeddata output
lines which are connected
to the latchjdecoderjdriver IC
corresponding to that
decade,
i.e.,
UlO?, Ul09,
Ulll and Ul13.
Each of
6-2
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