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This mirror output is input to CX23035 CNIN pin
©) then is divided into 41 and output from SENSE
pin (18) to the mechanism
control IC SENS pin Q2.
(At this time, it is divided and can be read.)
This
input signal is counted by the mechanism
control IC
at rise or fall and is converted to the number of tracks
to be jumped.
For example, for a 1000 track jump,
consecutive cmparison, such as 1000/82 = 12 is done
and when that value is reached, each servo is turned
on and the optical pick-up is braked.
Then DATA-Q
is read, converted to track number, and if within a
certain range,
100, 10, 1 track jump are performed
and
convergence
is done.
Outside
of that range,
direct search is performed again.
CX 23035
CX20109
data
RF amp
demodulation
1c 101
=
1Cc601
4 } Mirror output
is input to CX23035.
digital
filter
Optical
pick-up
CX20108
The divided signal
enters mechanism control IC.
Mechanism control IC counts that signal.
Mechanism
control 1C701
Q@ search command is output.
}
Master Control
1C702
computer
C1) Key input or remote control input.
Frame Structure of EFM Modulated Recorded Signal
iframe (588 bits)
=
a
Q
frame sync signal
:
;
:
;
TH bits] 1 bite 2 bis SYNC (frame sync)
= 24 bits + 3 bits (coupling bit)
1
0
1
User's bit (P-W)
14 bits + 3 bits (coupling bit)
or
Data symbol
11 bits(11 bits 2 bits
Parity symbol
(6)
1
| 0
1 Frame
= 588 channel bits
parity
D/A converter
low pass filter
Data Q is constantly input to [C303 during play.
@ When mechanism control IC finishes counting, each servo
is turned on and the sled motor is braked.
4) Tracking, sled servo OFF.
Focus servo ON, sled motor moves.
|
:
|
7) is performed again and next track jump is determined.
(3) Difference between present address and address to be jumped to is
converted to track number.
If far away, direct search is done.
24 x (14 bits + 3 bits (coupling bit))
6 samples for each left & right group
8 x (14 bits + 3 bits (coupling bit))
CDP-502ES/620ES | CDP-502ES/620ES —
The CD player can read out (1 frame (588 bits) x
98 frames x 75) in one second. 98 frames x 75 = 7350
SYNC (frame sync signal) identifies the beginning
of the frame during playback, and is for frame sync,
and a 24 bit pattern is used so that it will not be
generated during other signals.
The time of 1 frame is 136.05 usec (1/7350), so
the frame repeat frequency is 7.35 kHz.
This sync
signal is applied to mechanism control pin
during
frame sync lock.
The
channel
bit frequency
is 7.35 kHz x 588=
4.3218 MHz.
The user's bit, of which there is one symbol in >
each frame, is called a subcode, and 98 symbols are
gathered to form one data block (subcode frame).
The subcode has 8 channels, P, Q and R — W, and
the 8 bits in one symbol
are composed
of one bit
from each channel.
P is used as selection dividing mark, and Q is used
for TOC
(Table of Contents) at the lead-in area and
for the mode control signal preemphasis and also for
display
and
address
data of track
number
(TNO),
index
number,
playing
time
and other information
during a selection.
The data is renewed
for each of these every 98
frames, or every 1/75 seconds.
EFM converts 8 bit data to 14 bits and modulates.
For 8 bit data 1 and 0, there. are 2° = 256 combi-
nations, and for 14 bit data, it is 2*4 = 16384.
For EFM, relative to the 8 bit data pattern, "'more
than 2 0's between bit 1 and 1, but less than 10" is
selected from the 14 bit data pattern.
3 bit coupling bits are inserted between the con-
verted 14 bit blocks.
1 symbol 8 bit data bit includes
a coupling bit and is converted to 17 bits.
The con-
verted bit is called a channel bit.
When
14 bits and 14 bits are coupled, the coupling
bit has more than two 0's.
LINE
OUT
1C352 D/A Converter
A 16 bit serial signal is input to pin
(DIN) as
the data.
The data synchronizes to the rise of pin
(BCLK) and is taken into the IC from the MSB, in
order.
:
At the 17th fall of BCLK, if pin (8) (WCLK) goes
from high to low, the 16 bit data is transferred from
the shift register to the latch.
Each channel's data is taken in from the 17th one.
When pin (11) (LRCK) is low, R-CH data is taken in.
When pin (i) (LRCK) is high, L-CH data is taken in.
Data output is R-CH signal output from pins
(IOUTL) and @3) (DCL) when LRCK is low.
When
LRCK
is high, R-CH signal is output from
pins (7) (IOUTR) and (3) (DCR).
The data transferred to the latch is set in the coun-
ter.
Current flows from ICOUTL or ICOUTR
by inte-
grated current start signal, but the counter determines
the flow time.
Data
is preset
in the counter,
and counting
is
started from
that value.
After counting, and after
counting offset, output is stopped by the integrated
current stop signal.
In
this
way
the
digital
signal
is converted
to
analog.
DCR
and
DCL
are
for
discharging
the voltage
charged during integration and are output before inte-
grated current start.
Q301 and Q401 are FET for discharging.
1C355
1C355
performs signal switching, and«switches L-
CH and R-CH alternately at high speed; Bet
ae
The truth table is shown below. On: this set A.and
C are connected, so there are only two methods of
use, () and Q).
2
IC352 pin (1) (LRCK_OUT) is connected to:
1C355_ pins (9) (C) and (1) (A), and LRCK OUT
signal is output synchronized with LRCK,
and this' ©
signal switches L-CH and R-CH.
:
Truth Table
CONTROL INPUTS
Pins which
INHIBIT
leo
a
L | 0X,0Y,0z
1X, OY, 02
0X, 1Y, 0Z
1X, 1Y, 0Z
0X, OY, 1Z
1X, 0Y,1Z
. a
1X, 1Y,1Z
Bye
| eee
rpc
oper
=|
a
H
L
H
L
H
myeye
"|
xo}
a
Ki)
oOo}
x
Aree
mene.
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