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CDP-C20/C26/C30
CDP-C20/C26/C30
SECTION 4
DIAGRAMS
4-1.
IC BLOCK DIAGRAMS
IC1
CXA1081S
IC201
CXD1161P
IC2
CXA1182S
CH 2 OUT
NC
Vref
Le
'
o
2
8
& &
(%) DIRC (3)
C - OUT (Y) AVEE
(=) TST
OUT
@-@
3.5V_ REGULATOR
a
«
=
48)
(=) GND
(@) V ref LI
G) GND
DA
=
12 L OATA REGISTER
INPUT SHIFT
REGISTER
ADDRESS
DECODER
2 Le TIL
R- STRING
LEVEL
SHIFT
TIMING
OUTPUT
DECODER
DAC
DAC
OAC
CONTROL
s
za
=
s¢
FSI-4
PEAK
BOTTOM
S
i)
HOLD
HOU!
MIRROR
©)
©
HO
(3)——(4)
(7)
(9)~(10)
GINO
Q.
. _J
TRACKING
PHASE
g
-
-_
~
°
Nx
=
a=
ia
O
COMPENSATION
>
=x
x
2
"xO
x
-
Uo
8S
°
_—
a
>
ae
xo
>
2
©
rg
2 _
S
a
M7
AN
a
Fas
>
>
FOCUS PHASE
=
COMPENSATION
FSI
FS2
=
DEFECT = OO | LHX
A
ne Pi ee ete
fet moe
no
| 1
1/@---|-------------|---
Q
aortom T PP
HOLO
vy
eee
Lo
Assen ®)
TRACKING
Ic9
M5294P
»_
ERROR AMP
i
WE
bh
moO
te
8
e
>
oc
>
S
we
HT
>
©
ip
S
in
mo.
Ak
+
>
+
z
of
3S
BES
ws
MIOPOINT
VOLTAGE
(6
(9
BUFFER
HEAT INTER:
CEPTION
CIRCUIT
STAND
A
a
im?
DELAY "
TS
>
CURRENT
I
CONTROL aa
es He el
mre
al
CURRET
REST-
DELAY
=
iran
ciRoUN
©
>
S.
ine)
+
+5V
DELAY
PHASE
CAPACITY
REVISION
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