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2. CONTROL SECTION
2-1 CPU (1C102)
1) Specification
The KX-B620/B520 Series uses a single-chip 4 bit
CMOS microcomputer.
Its specification is as follows.
@ INSTRUCTION EXECUTION
Si NIB. tiene
arts esnmeniNeSS 'dein
@ MEMORY ROMersesreeessessees 4,096 word x9 bit
ae
eee
ee 956 word X4 bit
@ TIMER
TIMER
cocccccecctceccrecsecees 9 bit timer
TIMER2 --8 bit timer /event counter
TIMERS ---8 bit timer /event counter
ST IRAERA
a ieuekissuneteeasnl 8 bit timer
@ INTERRUPT SIGNALS :**----* 4 (external, timer,
serial 1/0 timer2)
@ ANALOG INPUT (Port K)
crrsseressestesereestesees 4°
© 1/0 PORT (Port D, F, GS)
strsseeesseseseees 7
@
TIMER
{7/0
(CNTR)
Prererrerrer rere errr ere reer eee tre 1
@ SERIAL |/O ceevrecesseseseeetsesteseseeeeeseneenes 8 bitx1
2) Circuit Operation
(CPU Main Function)
Thermal head strobe and latch signal
production
S)
Screen feed motor drive pulse production
Paper feed motor drive pulse production
Lamp drive signal production
LED turn on signa! production
Key input accept
9 © @®@
8 © 8
Start signal production to memory the WHITE
waveform of the blank area of the screen.
KX-B620 Series
KX-B520 Series
Signals production described below
CCO signal is made by using Timer 1, and
Timer 2.
CCO signal is used by Gate Array 1C103 to
make line start signal INT.
it interrupts CPU, and CPU starts 1 line
sequence synchronizing with this, so almost all
other signals are synchronizing with this
signal. ENBIM signal "H" means available
interval of the signal from the analog video
circuit.
PAPW signal "H" means available interval of
the signal HDATA, which is fed to Thermal
Head.
When PAPALL signal is "L", the clock CLKHD
is stopped to feed to Thermal Head.
RESET—~L1J
vob (5V)
INT—~[_2]
41] ~—— CNTR
AVss
| 40] ~—— XIN
VREF—={_ 4)
[39] —=— Xout
Ko—e| 5]
38] <=
G3
Ki—~ | 6]
—-
G2
K2—|
7]
ad
| 36| —<——
G1
K3—~{_ 8]
S
| 35| <=
Go
AVbpD
8
| 34) —~
F3
So—>[70]
x
a3] = F2
Si
[11
x
=< Fi
S2—>[12|
x
[31] <= Fo
$3-<-=| 13]
a
| 30] ~<-
D0
S4—e| 14)
| 29| =
Do
S5———>| 15}
| 28} ~~»
Ds
Se
16]
—~—-e
27
S717]
[26] <-> De
Do»
18]
| 25| ~<—e- D5
Di~-—| 19]
| 24] =e
D4
(OV) CNVss
al as Bs
(OV) Vss
[22] ~~»
D2
CPU Outward Form
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