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The ADC device is programmable through the serial programming interface (SPI) bus accessible through
the FTDI USB-to-SPI converter located on the EVM. A GUI is provided to write instructions on the bus and
program the registers of the ADC device.
For more information about the registers in the ADC device, see the ADC12J2700 and ADC12J1600 data
sheet (SLAS969) .
4.1
Supported JESD204B Device Features
The ADC device supports some configuration of the JESD204B interface. Due to limitations in the
TSW14J56EVM firmware, all JESD204B link features of the ADC device are not supported.
the supported and non-supported features.
Table 4-1. Supported and Non-Supported Features of the JESD204B Device
JESD204B FEATURE
Number of lanes per channel
(L)
Number of frames per
multiframe (K)
Scrambling
Test patterns
Speed
(1)
Dependent on bypass or decimation mode and output rate selection
4.2
Tab Organization
Control of the ADC device features are available in the EVM, JESD204B/DDC, NCO Configuration, Bank
Correct, and Low-Level View tabs.
4.3
Low-Level Control
The Low-Level tab, listed in
time, the following controls can be used to configure or read from the device.
CONTROL
Register map summary
Write register button
16
Device Configuration
SUPPORTED BY ADC DEVICE
(1)
L = 1, 2, 3, 4, 5, 8
(1)
K
= 2–12
min
K
= 32
max
Supported
PBRS7, PBRS11, PBRS15,
Ramp, D21.5, K28.5, Repeat ILA, supported.
Modified RPAT, Long/Short
Transport, Serial Out 0, Serial Out
1, Bypass Lane ID, Bypass ADC
(1)
Data
(1)
Lane rates from 1 to 10 Gbps
Figure
4-1, allows configuration of the devices at the bit-field level. At any
Table 4-2. Low-Level Controls
Displays the devices on the EVM, registers for those devices, and the states of the registers
• Clicking on a register field allows individual bit manipulation in the register data cluster
• The value column shows the value of the register at the time the GUI was last updated
• The LR column shows the value of the register at the time the register was last read
Write to the register highlighted in the register map summary with the value in the Write Data field
Copyright © 2014, Texas Instruments Incorporated
Device Configuration
SUPPORTED BY TSW14J56EVM
L = 1,2,4,8 supported
L = 3 and 5 not currently supported
Most values of K supported, constrained by requirement that K
n
× F = 4
Supported
ILA, Ramp, Long/Short Transport and Bypass ADC Data
Other patterns not supported at this time.
Lane rates from 2 to 10 Gbps currently supported.
ƒ
parameter must be properly set in HSDC Pro GUI.
(SAMPLE)
DESCRIPTION
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Chapter 4
SLAU560 – August 2014
Table 4-1
lists
SLAU560 – August 2014
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