Pioneer DV-45A Service Manual page 119

It input a FSX signal from a CD decoder.
FSX signal is 7.35Khz at normal speed with frame alignment signal of error correction of
CIRC.
By setting of a $7F register, It become the internal monitor output (STATUS 4).
It input an EFLG signal from a CD decoder.
An EFLG signal is a monitor signal of error correction processing movement of CIRC.
By setting of a $7F register, It become the internal monitor output (STATUS 3).
It is analog RF signal input terminal to built-in A/D converter.
136 FSX/STATUS4 Vo
It is reference voltage input terminal of built-in A/D converter.
OUT |Connect with VRT.
179 SBSO
184 EXCK
< D >
It is center voltage output terminal of built-in A/D converter.
VRB } IN | It is reference voltage input terminal of built-in A/D converter.
VRBS Connect with VRB.
CKE/PD3 It is an Enable signal of SDCLK.
CSB/PD2 It is chip select signal of SDRAM.
YBa | SDCLK It is a terminal outputting a movement clock of SDRAM.
| 68 ~~ [XCASH/DOMH When it uses DRAM of bus 16 wide bit, it is a CAS signal of high rank 8bit.
197 VREQEN/PD1 vO It is an Enable signal of Video-REQ.
198 AREQEN/PDO vO It is an Enable signal of Audio-REQ.
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