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1-4. Circuit Description
PR-337 Board
The PR-337 board consists of a power supply circuit, video amplifier circuit, low-pass filter (LPF), A/D
converter circuit, video signal processing circuit, clock generator circuit, tally control circuit, and micro-
processor.
(1) Video signal processing
The analog HD Y/Pb/Pr signal input from CN1 is passed through a video amplifier (IC201, IC202, and
IC203) and LPF (IC204). After that, the signal is converted into a 10-bit digital signal of 74 Mbps using
an A/D converter (IC301) and output to FPGA (IC401).
FPGA discriminates the format of an input signal using the H/V sync signal generated by a sync separator
IC (IC206), and outputs the H/V sync signal (by adding PLL to the sync signal) to the A/D converter.
FPGA also distributes the input HD Y/Pb/Pr digital signal input from the A/D converter to two lines. The
distributed digital signal is peaked respectively and output to an image processing IC (IC801).
The image processing IC converts image size and IP and also converts the input HD Y/Pb/Pr digital signal
into a Quarter HD RGB digital signal. It also sets brightness and contrast and synthesizes two screens.
The qHD RGB digital signal output from the image processing IC is input into FPGA again. FPGA knee-
corrects an input signal, superimposes an OSD signal, and outputs it to an LVDS transmitter (IC1101).
The LVDS transmitter converts each 10-bit digital signal of RGB and sync signal into an LVDS signal
and outputs it to CN8.
(2) Internal test signal generation
The FPGA (IC401) has internal test signal generator circuits (two in the first-half part and one in the
second-half part) and performs switching with a main-line signal.
(3) Control system
CPU (IC1201) mutually communicates with FPGA, and image processing IC by serial communication. It
also sets the parameters of the LPF, A/D converter, and clock generator IC (IC481) by I
tion. Moreover, the CPU controls a panel module.
The brightness, contrast, and peaking volume level signal lines are connected to the A/D input port of the
CPU so as to control them.
The D/A output port of the CPU controls the luminance of the up-tally lamp.
The FPGA (IC401) controls the luminance of a tally and indicator using the PWM control and performs
I2C communication with the connected camera.
(4) EEPROM
The setting data and the current conduction duration of this unit are recorded in EEPROM (IC1302) on
the PR-337 board. The model information such as the serial number of this unit is recorded in EEPROM
(IC1305).
(5) Power supply circuit
The power supply circuit of the unit operates in the proper input voltage range and has 14 outputs includ-
ing one circuit directly connected to the UNREG power supply.
. Inrush current/reverse connection/backflow/transient burst prevention circuit
The circuit consisting of an FET (Q1402) immediately after UNREG_IN, a transistor (Q1401), and
peripheral parts prevents inrush current, reverse connection, backflow, and transient burst.
Inrush current is reduced by gradually activating the gate by the current flowing through the Q1402
body diode.
HDVF-EL70/HDVF-EL75
C communica-
2
1-5
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