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Hardware
2.7 DS320PR410 EVM Global Controls
Table 2-7
shows DS320PR410-RSC-EVM global controls that affect all devices on the board.
COMPONENT
J1
J2
J3
J4
J5
J6
J7, J8, J9, J10
J11
J12
J13
J38
J41
J44
J45
8
DS320PR410-RSC-EVM Evaluation Module
Table 2-7. EVM Global Controls
NAME
FUNCTION / DESCRIPTION
MODE control tied to MODE pins of all eight DS320PR410 devices on the EVM
L0: All devices set to Pin Mode (Default)
L1: All devices set to SMBus / I
4x2 Header
L2: SMBus / IC Secondary Mode
L3: Reserved
L4: Reserved
RX_DET control tied to RX_DET pins of all eight DS320PR410 devices on the
EVM
L0: RX Detect state machine disabled on all devices
L1: RX Detect state machine enabled on all devices (3 valid detections needed)
4x2 Header
L2: RX Detect state machine enabled on all devices (2 valid detections needed)
L3: Reserved
L4: RX Detect state machine enabled on all devices (1 valid detection needed) -
Default
2
SMBus / I
C interface. All eight DS320PR410 devices on the EVM are on the same
5x2 Header
bus and can be accessed through this interface.
PWDN control tied to PD pins of all eight DS320PR410 devices on the EVM.
Remove shunt on J6 when using J4 to control PWDN.
PWDN tied to GND: All devices enabled (Default)
PWDN tied to PERST_INV: All device PD pins controlled by inverted PCIe Reset
3x2 Header
(PERST#)
PWDN tied to 3.3V_REG: All devices disabled.
PWDN floating: Tie PCIe system PRSNT signal to PWDN using J6 for the PWDN
control (optional for PCIe use case)
Access point to the WP (write protect) pin of the onboard EEPROM devices.
3x1 Header
WP tied to GND: I
WP floating: I
Alternative PWDN Control. Remove shunt on J4 when using J6 to control
PWDN.
2x1 Header
PWDN floating: Use J4 for the PWDN control (Default)
PWDN tied to PRSNT: PRSNT signal controls PWDN (optional for PCIe use case).
PCIe PRSNT Signal Controls
Tie pins 1-2 on J7, J8, J9, and J10: Allow support any PCIe bus width (Default)
Tie pins 2-3 of J7, leave J8, J9, and J10 floating: Force x1 PCIe bus width.
3x1 Headers
Tie pins 2-3 of J8, leave J7, J9, and J10 floating: Force x4 PCIe bus width.
Tie pins 2-3 of J9, leave J7, J8, and J10 floating: Force x8 PCIe bus width.
Tie pins 2-3 of J10, leave J7, J8, and J9 floating: Force x16 PCIe bus width.
Onboard regulator input. Apply 12 V when using the EVM as a standalone system.
2x1 Header
DO NOT APPLY power if plugging the EVM into a system as the power is provided
through the gold finger connector (CONN1).
2x1 Header
Access point to the GND reference.
2x1 Header
Onboard 3.3 V output.
2
3x1 Header
Select I
C adapter to plug into Connector J3.
Tie pins 1-2 for TI USB2ANY Adapter
Tie pins 2-3 for Aardvark Adapter (Default)
Select the appropriate jumper position for the selected adapter to avoid
damaging the EVM.
3x1 Header
READ_EN_N select
Tie pins 1-2 to tie READ_EN_N to GND and initiate EEPROM read (EEPROM
mode only) - Default
Tie pins 2-3 to tie READ_EN_N to disable EEPROM read
2x1 Header
SMDAT header to connect global SMBus Data line (Pin 1) to local SMDAT/SDA
(Pin 2). Remove shunt to disconnect global SMDAT from local SMDAT/SDA.
2x1 Header
SMCLK header to connect global SMBus Clock line (Pin 1) to local SMCLK/SCL
(Pin 2). Remove shunt to disconnect global SMCLK from local SMCLK/SCL.
Copyright © 2023 Texas Instruments Incorporated
2
C Primary Mode (EEPROM Mode)
2
C Access to the EEPROM enabled
2
C Access to the EEPROM disabled (Default)
www.ti.com
SNLU334 – DECEMBER 2023
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