Sony UP-21MD Service Manual page 49

4-1-5. Memory Coniroi Biock
A four-dot pixel is stored in one address for high-speed processing using SDRAM of 32 bits in the
direction of depth so as to double the apparent SDRAM access speed. This processing is performed using
a standard cell circuit. The circuit is controlled by CPU.
Conversion of 8 bits to 32 bits and vice versa in case of input image data capture (FULL)
The eight-bit image data input to this circuit is stored in each line buffer in the order below.
LB Address Ao At A2 As <A4& AS Ab A7> AB
[bo | pr | ps | bs | Dis | Der | bee | bos | Doe |
[be | ps | 10 | bis | Die | Die | be | tr | oe |
[bs | ps | biz | pis | be | bas | se | 2s | De |
[0s | D7 | v4 | bis | bee | bz | bso | as | Dae |
LINEBUFFER1
LINEBUFFER2
LINEBUFFER A
LINEBUFFER3
LINEBUFFER4
The write operation of
LB1, LB2, LB3, and LB4 Switched for
is switched every two dots. each HD signal.
DRAM DATA
LINEBUFFER1
LINEBUFFER2
. LINEBUFFER B
LINEBUFFER3
LINEBUFFER4
LB is read as 32-bit d
ata and sent. to DRAM.
ParsrSrararsrersrars
a ety
The number of addresses in LINBUFFER is one-fourth
of the number of input image data items.
DRAM Address Ao At A2 A3 A4& AS Ab A? AS
The main operation and setting of a DRAM control circuit are as follows:
* Various capture operations
FULL image
SPLIT 2 image
SPLIT 4 image
Capture shift size
Write DRAM address
By setting the items above, the DRAM control circuit automatically performs the capture operation in
synchronization with VD and HD signals.
* Print data output operation
Number of output data items
Read DRAM address
The print data output operation is performed by setting the items above and by triggering from CPU.
UP-21MD V1 4-11