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Schematic Diagrams
System Block Diagram
CLICK BOARD
6 -7 1- W2 40 2-D 01
AUDIO BOARD
U SB +E AR PH ONE +E XT .M IC
6 -7 1- C4 50 8-D 03
POWER SWITCH BOARD
P OW ER S WI TCH +H OT KE Y X 3
6 -7 1- E5 1Q S-D 02
EXTERNAL ODD BOARD
E XT . OD D
6 -7 1- E5 1Q N-D 01
Sheet 1 of 43
CLICK BOARD
T OU CH P AD
System Block
S yn ap ti c
Diagram
810602-1703
I NT . K/ B
S AT A HD D
B - 2 System Block Diagram
Huron River System Block Diagram
Sandy Bridge
PROCESSOR
rPGA989/988
FDI
HD MI
0. 5" ~6 .5 "
<1 5"
CR T CO NN EC TO R
INTERNAL
CR T S WI TC H
CougarPoint
GRAPHICS
Platform
L CD C ON NE CT OR ,
<8 "
INTERNAL
Controller
L VD S S WI TC H
GRAPHICS
Hub (PCH)
32.768 KHz
E C
S PI
25x25x0.6 mm
IT E 85 18 E
989 Balls FCBGA
128pins LQFP
14 *14*1 .6 mm
33 MHz
LPC
0. 5" ~1 1"
B IO S
S PI
EC SMBUS
TH ER MA L
S MA RT
S MA RT
SE NS OR
F AN
B AT TE RY
32.768KHz
W 83 L7 71 AW G
SATA I/II 3.0Gb/s
< 12 "
USB P OR T
SA TA O DD
(U SB 0)
Memory Termination
800/1067 MHz
DDR3 / 1.5V
37.5*37.5 mm
SYSTEM SMBUS
0 .1 "~1 3
DMI*4
<= 8"
RJ-11
AZALIA
MDC
MODULE
MD C CO N
AZALIA LINK
PCIE
100 MHz
Mi ni P CI E
S OC KE T
USB2.0
3 G CA RD
480 Mbps
( US B9 )
1" ~1 6"
(Optional)
U SB P OR T
US B PO RT
C CD
(U SB 1)
( US B9 )
(U SB 5)
A UD IO
B OA RD
VDD3,VDD5
5V,3V,5VS,3VS,1.5VS,
1.5VS_CPU
1.5V,0.75VS(VTT_MEM)
1.8VS
DDRIII
SO-DIMM0
1.05VS, 1.05VS_VTT
DDRIII
SO-DIMM1
VCORE, 0.85VS
VGFX_CORE
AU DI O BO AR D
MIC
HP
IN
OUT
INT SPK R
Az al ia C od ec
INT SPK L
VIA VT1802
INT MIC
24 MHz
<1 2"
Mi ni P CI E
JMICRO
S OC KE T
JMC251 C
WL AN
( US B2 )
LAN
CARD READER
7I N1
RJ-45
S OC KE T
25
MH z
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