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9.
IC INFORMATION
CT-S520, CT-S420
¢ The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
1.
PD4443A (IC701)
System Control (CPU)
@ Pin Function
FL segment output (*1)
A/D 5-bit level scan output (*2)
Key scan output (*3)
5
XPOFF
| POWER OFF detection L (L: EDGE)
FIN
Level scan input for the 1/f high
frequency level
POWER KEY input detection ¢ (L:
7
POWER
EDGE)
TAKE-UP side reel sense input.
e
SENT
For the auto stop electronic counter
Supply side reel sense input.
For measuring the remain counter.
Lch level scan input
KEYO
[er
KEY3
BIAS _| Bias oscillation drive. H: ON
SYNC
CD-SYNCHRO code in detection. L: IN
4-bit key scan input (L: EDGE)
CONT to CD (for CD-SYNCHRO)
| 20 | MTRS
Meter amplifier gain selection.
Data input from the memory IC
ea
DATO | (NMS3C4sN).
22
DAT1
Data output to NM93C46N and LC7570.
Clock for communicating with
NM93C46N and LC7570
Chip select for communicating with
NM93C46N
Data latch for communicating with
LC7570
XBLK
L CONT of all outputs of LC7570
XLMU
LINE MUTE. L: ON
23
24
25
26
27
| 28 | XRMU
REC MUTE. L: ON
TEST signal output for the auto BLE
29
OSC | (400 Hz, 3 kHz, 15 kHz)
Ta
|
— i Clock input for the CPU (4.19 MHz)
SCK
cs
WR
To GNDC
Motor CONTs for the door and reel
Ree! motor PLAY torque selection.
H: ON
Mechanism capstan motor driving.
H: ON
For resetting the CPU. L: Resetting
Output for the FL grid
| so | stay | nas cists for the POWER STANDBY.
Solenoid driving for the mechanism.
(eee
cone ere
| 52 | mcr
Motor CONTs for the door and ree!
NRSO
1 bit of the 2-bit Dolby NR selection
FL segment (*1)
VLoAD
For FL. VF
CPU internal FL output buffer power
supply (Approx. -4V)
VPRE
FL segment output (*1)
FL segment output (*1)
Key scan output (*3)
FL segment output (*1)
Level scan (*2)
Key scan output (*3)
pa fe [we
*1: To the FL
*2: To the anodes D541 to D545
*3: To each key and SW
29g
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