Yamaha YMF795 Manual

Automobile sound player-2

Hide thumbs

Table Of Contents

Table of Contents

Quick Links

Download this manual

Outline

YMF795 is a sound source LSI to reproduce high quality melody and effect sound for in-car product. Yamaha's original

FM synthesizer embedded as a sound source can create various timbres, and also a sequencer embedded can

simultaneously generate up to four sounds with four different timbres without giving load to the controller.

Serial port is prepared as a controller interface, and no restriction of data capacity is present because melody data is

reproduced in real-time through FIFO.

A built-in amplifier to drive the dynamic speaker with 500mW power allows connecting a speaker directly.

This LSI is equipped with an analog-output pin also for the earphone jack.

In addition, supporting the standby mode can reduce the consumption current to 1 µA during the standby.

Features

YAMAHA's original FM sound source function

Built-in sequencer

Capable of producing up to 4 different sounds simultaneously (4 independent timbres available).

500mW output speaker amplifier

Sound quality correcting equalizer circuit

Serial interface

Arbitrary frequency of input clock from 2.685 MHz to 27.853 MHz in 55.93 kHz steps, as well as 2.688, 8.4, 12.6, 14.4,

19.2, 19.68, 19.8, and 27.82 MHz clock inputs

Analog output for earphone

Power-down mode (Typ. 1µA or less)

Supply voltage (Digital and Analog): 3.3V±10 %

24-pin SSOP. The plating of pins is lead-free. (YMF795-EZ)

YAMAHA CORPORATION

YMF795

APL-2

Automobile sound Player-2

YMF795 CATALOG

CATALOG No.:LSI-4MF795A20

2005. 11

Table of Contents

Summary of Contents for Yamaha YMF795

Page 1 Automobile sound Player-2 Outline YMF795 is a sound source LSI to reproduce high quality melody and effect sound for in-car product. Yamaha's original FM synthesizer embedded as a sound source can create various timbres, and also a sequencer embedded can simultaneously generate up to four sounds with four different timbres without giving load to the controller.
Page 2: Table Of Contents
YMF795 Contents ■General Description of YMF795 ........................3 ■Block Description ............................4 ■Pin Configuration............................5 ■Pin Description ............................. 6 ■Block Diagram.............................. 7 ■Register Map..............................8 ■Explanation of Registers..........................9 □Musical score data register ........................9 □Timbre data register..........................14 □Other control data ..........................17 ■Power-down control division diagram......................
Page 3: General Description Of Ymf795
YMF795 ■General Description of YMF795 YMF795 is controlled through the serial interface. Internal configuration the LSI has is shown below. Volume, power management, etc. SDIN Serial Timbre Data SYNC interface SCLK Timbre register Musical score Tempo data START/STOP Timbre allocation...
Page 4: Block Description
YMF795 ■Block Description 1) Serial interface block The block receives serial data and then identifies its Index data to send control data to each function block. 2) FIFO block FIFO temporarily stores musical score data. Musical score data up to 32 can be stored. The musical score data are processed in the sequencer when they are generated as sounds and those processed are deleted one after another.
Page 5: Pin Configuration
YMF795 ■Pin Configuration TESTO CLK_I <NC> /RST SDIN /TESTI SYNC /IRQ SCLK DVDD <NC> DVSS AVSS SPOUT2 VREF SPOUT1 HPOUT SPVSS SPVSS AVDD AVDD < 24-pin SSOP TOP VIEW >...
Page 6: Pin Description
YMF795 ■Pin Description Function CLK_I Clock input pin Be sure to use in no-connection. <NC> The pin is nowhere connected in the chip. SDIN Serial I/F data input SYNC Serial I/F synchronous signal input SCLK Serial I/F bit clock input Be sure to use in no-connection.
Page 7: Block Diagram
YMF795 ■Block Diagram Timing Generator HPVOL -step SCLK FMVOL Register -step SYNC Synthesizer Serial VREF − Simultaneous SDIN FIFO sound generation 16b×32w 4-tone /IRQ SPOUT1 SPVOL -step SPOUT2 VREF /RST VREF SPVSS Concerning AIN signal inputted into equalizer circuit It is possible to make the analog mixing between synthesizer output and other analog...
Page 8: Register Map
YMF795 ■Register Map Index Description $00h BL1 BL0 NT3 NT2 NT1 NT0 CH1 CH0 VIB TK2 TK1 TK0 Note data CH1 CH0 Rest data VCH2 VCH1 VCH0 VCHE $10 - 2Fh ML2 ML1 ML0 VIB EGT SUS RR3 RR2 RR1 RR0 DR3 DR2 DR1 DR0 AR3 AR2...
Page 9: Explanation Of Registers
YMF795 ■Explanation of Registers The YMF795 has three types of control registers: musical score data, timbre data, and other control data. □Musical score data register $00h Musical score data The musical score data are written into the 32-word FIFO. There are two types of musical score data: note data and rest data.
Page 10 YMF795 NT3 - NT0 : Pitch setting Four bits from NT3 to 0 are used to specify the pitch. The bit assignment is as follows. NT[3:0] Pitch Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited About “Setting Prohibited.” Although LSI never hangs, unusual sound may be generated. Never set it.
Page 11 YMF795 TI3 - TI0 : Interval setting These bits are used to set the interval time before the processing of the next note and rest. The interval “48” represents the time for the whole note. TI [3:0] Interval TK2 – TK0 : Note (sound length) designation These 3 bits are used to designate the note (sound length).
Page 12 YMF795 ■ ■ Caution When KEY is turned on again while release rate is not completely finished yet in the same channel, timbre may change. This happens in both sustained sound and decaying sound. The reason why it happens is that both envelope and phase in the career side and modulator side of the FM sound source deviate.
Page 13 YMF795 Default: 0000h Rest data Index $00h CH1 CH0 VCHE TI3 VCH2 VCH1VCH0 CH1 - CH0 : Part setting Using CH1 or 0 bit, set the part of each rest. CH[1:0] Part designation TI3 - TI0 : Interval setting These bits are used to set the interval time before the processing of the next note and rest.
Page 14: Timbre Data Register
YMF795 □Timbre data register $10 – 2Fh Timbre data Eight timbre data can be registered into the register and four data out of them can be simultaneously reprodu ced. Timbre is made by setting both [parameters for the modulator] and [parameters for the carrier].
Page 15 YMF795 VIB : Vibrato This bit is used to set ON/OFF of vibrato function. “0” for OFF, “1” for ON. The vibrato frequency is 6.4 Hz and the modulation depth is ±13.47cent. EGT : Envelope waveform type This bit is used to select the type of the envelope waveform.
Page 16 YMF795 SL3 - SL0 : Sustain level setting The Sustain Level, in the case of decaying sound, is the transition level from the Decay Rate to the Release Rate, and in the case of sustained sound, is a level held.
Page 17: Other Control Data
YMF795 □Other control data $30h Timbre allocation data One piece can be generated at the same time up to four parts, and timbre can be assigned for each part. The data is used by allocating four timbres out of eight timbres registered in the timbre data register to each part.
Page 18 YMF795 $33h Clock selection Default: 0000h Index $33h CLKSEL This register is used to set the clock frequency inputted through CLK_I pin when making the clock setting in the preset mode. A clock with any frequency can be input during the reset period.
Page 19 YMF795 $35h Speaker volume control $36h FM volume control $37h Earphone output volume control Default: 0000h Index $35-7h These bits are used to set the volume of each source. The volume setting consists of 31 steps and MUTE state, and can be set in 1dB steps.
Page 20 YMF795 $39h Clock setting Default: 0000h Index $39h CLKSET The register is used to set the clock frequency that is input through the CLK_I pin when the setting is made in the programmable mode. Be sure to complete the setting before its sound generation.
Page 21: Power-Down Control Division Diagram
YMF795 ■Power-down control division diagram Power-down of the LSI can be controlled for each divided internal function. The power-down is controlled by Index 38h. Controlled by Controlled by Controlled by using DP bit using AP2 bit using AP4 bit Timing Generator...
Page 22 YMF795 This is the bit to power off the inverted amplifier side of the speaker output section. Turning the inverted amplifier side power on after turning the VREF circuit and a non-inverted amplifier power on can reduce pop noise. This is the bit to power off the DAC and the HP Volume section.
Page 23 YMF795 Example of the setting in each case. Depending on how the function is used, bit settings can be combined as shown below. Caution Analog section Be sure to set all volumes to “MUTE” first, whole power-down then set all bits to “1” simultaneously.
Page 24: On Reset
YMF795 ■On Reset This LSI can be initialized by setting /RST pin to “L.” And, CLR bit is provided in $32h to allow the software to initialize the LSI. Hardware reset initializes the LSI and returns it to the default condition.
Page 25: On Interrupt Sequence
YMF795 ■On Interrupt Sequence An interrupt from LSI (/IRQ-“L”) occurs when the amount of data in the FIFO becomes less than the setting value. For example, supposing that 10h (16b) is set to the IRQ point of $34h, the FIFO becomes full before starting a piece as described in “Settings and procedure required for a piece generation.”...
Page 26: State Transition
YMF795 ■State Transition The figure shown below is a state transition diagram of the YMF795. Digital PowerON Ready Analog PowerON Power On Ready Hardware Reset Power On Power Off Initialized Write Setup Data Analog STOP PowerDown mode FIFO Data Write...
Page 27 YMF795 Description of each state Digital Power ON Ready This is a state before turning on the digital power supply. Hardware Reset Input the hardware reset to the LSI in conjunction with the power-on of the digital power supply. Analog Power ON Ready This is a state before turning on the analog power supply.
Page 28: Operation In Fifo Empty Condition
YMF795 ■Operation in FIFO empty condition If FIFO become empty during reproduction the musical score data written last is processed continuously until the next data is written. If the last data written is a note data, that note is reproduced continuously.
Page 29: Example Of Peripheral Circuit
YMF795 ■Example of peripheral circuit Amp. Headphone SCLK SCLK SYNC SYNC SDIN SDIN YMF795 SPOUT1 RESET# /RST Speaker IRQ# /IRQ SPOUT2 0.1uF +3.3V AVDD CLK_I AVSS 4.7uF SPVSS +3.3V 0.1uF 4.7uF 0.1uF On /RST pin A schmitt circuit is not used for /RST pin in this device; therefore, please design a board in consideration of noise to the /RST line.
Page 30: Circuit Diagram And Wiring Diagram When Two Power Supplies Are Used
YMF795 Precautions for the use of separate power supplies: A LSI with multiple power supply inputs needs to pay attention to the followings for [Power supply connection] and [Ground connection]. We explain it here by giving an analog circuit power supply and a digital circuit power supply as an example.
Page 31: Circuit Diagram And Wiring Diagram When One Power Supply And One Voltage Regulator Ic Are Used
YMF795 (2) Circuit diagram and wiring diagram when one power supply and one voltage regulator IC are used: ・Be sure to connect VSS pin to AVSS pin near the LSI. Excessive inductance between VSS pin and AVSS pin may cause malfunctions and failures.
Page 32 YMF795 Warning for the device which makes sound through speaker A speaker radiates heat in a voice-coil by air flow accompanying vibration of a diaphragm. When DC signal (several Hz or less) is input, heat radiation characteristics falls rapidly. In addition, even if it is used lower than the rated input, it may lead to voice-coil burnout, smoke, or ignition of a speaker.
Page 33: Volume Level Adjustment In Monophonic Sound And 4-Sound Generation
YMF795 ■Volume level Adjustment in monophonic sound and 4-sound generation The volume level outputted from DAC varies depending on the number of the pronunciation. When one tone (*) is output from the FM sound source, output voltage amplitude from DAC becomes 0.4125 Vp-p.
Page 34 YMF795 Example of the recommended level adjustment in all the system Turn down either FM or SP volume a little as a default (-3 dB to -6 dB or so). This is made for previously assuring a volume of which Gain is increased, because either volume may be controlled...
Page 35: Sound Quality Correction Circuit
YMF795 ■Sound Quality Correction Circuit Sound quality and Gain can be corrected by using an external circuit connected to EQ1 to 3 pins. The internal circuit configuration of EQ1 to 3 pin and example of the external circuit are as follows.
Page 36 YMF795 Using a resister R3 can obtain the following frequency characteristic. VREF Gain1= (R2+R3) /R1. Gain2=R3/R1. Filter cutoff frequency of f1 and f2 is: f1=1/ (2π×R1×C1). f2=1/ (2π×R2×C2). Gain Gain1 Gain1-3dB Gain2 Freq -36-...
Page 37: Serial I/F Specifications
SDIN Index Data (8bit) Control Data (16bit) YMF795 is controlled by the three serial interface lines of SCLK, SYNC, and SDIN. Relation between SDIN and SCLK The LSI takes in the value of SDIN at the rising edge of SCLK.
Page 38: Electrical Characteristics
YMF795 ■Electrical Characteristics 1. Absolute maximum ratings Parameter Symbol Min. Max. Unit voltage (analog) AVDD -0.3 Supply upply voltage (digital) DVDD -0.3 Analog input voltage -0.3 AVDD+0.3 Digital input voltage -0.3 DVDD+0.3 Storage temperature °C Note) DVSS = AVSS= SPVSS = 0V 2.
Page 39 YMF795 4. AC characteristics Conditions: Input signal of V =0.8×DVDD, V =0.1×DVDD. Timing measurement at V =0.7×DVDD, V =0.2×DVDD. 4-1. CLK_I ,Reset Parameter Symbol Min. Typ. Max. Unit CLK_I clock period Tcclk_period 35.8 CLK_I “L” pulse width Tcclk_low CLK_I “H” pulse width Tcclk_high /RST active “L”...
Page 40 YMF795 4-2. Serial Interface Parameter Symbol Min. Typ. Max. Unit SCLK clock period Tsclk_period SCLK “L” pulse width Tsclk_low SCLK “H” pulse width Tsclk_high SCLK rise time Trise_sclk SCLK fall time Tfall_sclk SYNC “H” pulse width Tsync_high SYNC rise time...
Page 41 YMF795 5. Power consumption Parameter Min. Typ. Max. Unit ormal operation 2200 Digital part in n µ sound generation Analog part without Ω load Analog part at output 300mW In power-down mode µ Note) T =-40 to 85°C, DVDD= AVDD = 3.3±0.3V, Capacitor load=50pF 6.
Page 42 YMF795 FM Volume Parameter Unit Volume setting range Volume step width Decay rate in MUTE Minimum load resistance kΩ Maximum output voltage amplitude Vp-p Output impedance Ω Note) T =25°C, DVDD = AVDD = 3.3V HP Volume Parameter Unit Volume setting range...
Page 43: General Description Of Fm Sound Generator
YMF795 ■General description of FM sound generator “FM” stands for Frequency Modulation. The FM sound generator utilizes the higher harmonic wave produced by the frequency modulation for synthesis of the musical sounds With the use of this FM system enables a comparatively simple circuit to produce such waveform that has a harmonic wave including disharmonious sounds, it is possible to create a wide range of sounds from the synthesized sounds of the natural musical instruments to the electronic sounds.
Page 44: External Dimensions
YMF795 ■External dimensions -44-...
Page 45 YMF795...