Circuit Description - Heathkit mMATIC SA-5010A Manual

Memory keyer
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CIRCUIT DESCRIPTION

CONTROLLER
The SA-2010A Memory Keyer is controlled mainly by U1 which is a custom 3870 single-chip micro-
processor. This microprocessor services the keypad and paddles, determines basic keyer timing,
keys the sidetone and output circuitry, stores and retrieves data from the external RAM and up-
dates the status LEDs.
The 3579.545 kHz crystal (Y1) determines the frequency of the clock and its output is divided in-
ternally to provide a 500 µs basic timing interval. This time interval forms the dots, dashes, in-
terelement, intercharacter and interword spaces, which all depend on the speed, spacing and
weight for which the Memory Keyer is set from the keypad.
Capacitor C1 and an internal pull-up resistor provide a power-on reset to the microprocessor. Diode
D1 allows capacitor C1 to discharge quickly when the Memory Keyer is turned off.
Port 0 is an address bus for the external RAM, which consists of ICs U2 and U3. This RAM is a
message buffer memory and also stores the last-set keyer parameters.
Port 4 is the data bus for the external RAM and for the LED latch IC U7. This port has a strobe pin
that clocks data into either RAM or the latch, whichever is enabled, when data is output to this
port.
Port 5 is a multipurpose output that selects either the RAM or the LED latch for a "write" operation
or, enables RAM for a "read" operation (bits 6 and 7). It gates the sidetone to the speaker (bit 4)
and determines whether the keyer output will be keyed output will be keyed with the sidetone (bit
5). It also lowers the sidetone pitch when necessary (bit 3) and scans the three keypad columns
(bit 0, 1 and 2).
Port 1 inputs the key pattern from the selected column. Internal pull-ups cause all inputs to be
held high until a key is pressed. When you press a key in the selected column, the low level on the
column line is passed through the switch contacts to the associated bit in port 1. The key is recog-
nized by U1 and the appropriate action taken. The dot/dash paddles are effectively part of the key-
pad matrix, but are handled differently by the microprocessor.
The TUNE key is not part of the keypad matrix. It is connected to the external interrupt pin on
U1. This key is active only when the keyer is in "Normal" or "Paused" modes, and only when the
keyer has completed the last character sent. The keyer is then latched in the Tune mode until you
press some other key (or touch a paddle). At this time, the Tune mode is unlatched and that key
performs its normal function.
SIDETONE OSCILLATOR / TOUCH PADDLE CIRCUITRY
OR gate IC U9D, inverter U8B and their associated components form an astable oscillator. This os-
cillator runs continuously while the keyer is turned on the oscillator frequency is manually adjusted
with Pitch control R39. The output of this oscillator is gated through IC U9C by the microprocessor
to transistor Q13 which drives speaker SP201.
The output of the oscillator, which is buffered by transistors Q17 and Q18, also drives the "D" input
and clock input of flip-flop IC U11A and B. With paddle controls R12 and R13 properly set, the D
input will go high just in time for the rising edge of the clock to SET the flip-flops. When you touch
a paddle, your body capacitance is added to delay the D input enough that is still low when the
clock goes high, resetting the associated flip-flop. This turns the transistors Q2 and Q3 on and acts
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