LG -P940 Service Manual page 171

BASE BAND PROCESSOR
Boot Configuration
VSD2_1.8V
R401 R402
4.7K 4.7K
R403 R404
4.7K 4.7K
VBAT VBAT_CP
FB403 120
VSD1_1.3V
C423
0.1u
VSIM_2.9V
VUSB_IO_3.1V
VSD2_1.8V
VPLL_1.2V
VIO_1.2V
VUSB_PD_1.1V
VUSB_ANA_1.8V
C430 C431 C432 C433 C434 C435
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
LGE Internal Use Only
VSEL_1.8V
VBAT_CP
R417 R418
DSP_AUDIO_IN1
4.7K 4.7K
MON1
FB401
VBAT_CP
MON2
FB402
IFX_TRIG_IN
60
60
C414
10u
C415 C416
VSD2_1.8V
10u 10u
VSD1_1.3V
L401 3.3u
L402 3.3u
C418
TP410
22u
C419
22u
VSD2_1.8V
R408
R409
DNI 4.7K
B8
MEM_WP FWP
A6
MEM_BUSY/ FCDP_RBn
J14
MEM_CS0_N MEM_CS0_N
R410 J13
MEM_CS1_N MEM_CS1_N
4.7K
H14
MEM_CS2_N
H13
MEM_CS3_N
G10
MEM_ADV_N MEM_ADV_N
B13
MEM_RD_N MEM_RD_N
B12
MEM_WR_N MEM_WR_N
K17
MEM_WAIT_N MEM_WAIT_N
E14
DDR_RAS_N MEM_RAS_N
B7
DDR_CAS_N MEM_CAS_N
G14
MEM_BE0_N
G13
MEM_BE1_N
A12
MEM_BC0_N MEM_BC0_N
F16
MEM_BC1_N MEM_BC1_N
B10
DDR_DQS[0] MEM_BC2_N
G16
DDR_DQS[1] MEM_BC3_N
A14
MEM_SDCLKO MEM_SDCLKO
B15
MEM_BFCLKO_0
A15
MEM_BFCLKO MEM_BFCLKO_1
B14
DDR_CKE MEM_CKE
L7
MMCI1_CMD
M3
MMCI1_CLK
M5
MMCI_DAT_0
M2
MMCI1_DAT_1
M4
MMCI1_DAT_2
M6
CP_DOWN_CHECK MMCI1_DAT_3
N5
IFX_RTCK MMCI1_CD
K14
VDD_CORE_1
H9
VDD_CORE_2
C424 C425 C426 E10
VDD_CORE_3
0.22u 0.1u 0.22u E13
VDD_CORE_4
K9
VDD_CORE_3G_1
R8
VDD_CORE_3G_2
VSD2_1.8V
E12
VDD_CORE_EBU
K8
VDD_IO18_1
B11
VDD_IO18_2
F15
VDD_IO18_3
C427 C428 C429 N11
VDD_IO18_4
0.1u 0.1u 0.22u K11
VDD_IO18_5
J17
VDD_IO18_6
L8
VDD_MMC
T12
VDD_SIM
R16
VDD_USBIO
K16
VDD_MIPI
R411 4.7 R12
VDD_PLL
U15
VDD_IO12
N9
VPP
T15
VDD_USB_PD
P14
VDD_USB_ANA
T10
VDD_DIGRF
C438 10p L17
C436 F32K
C437 M17
0.1u
OSC32K
0.1u M16
X401 VSS_RTC
N17
FC-135
VDD_RTC
32.768KHz
C439 10p
VRTC_1.8V
C440 C441
220n 10u
DI3_RX_DAT
DI3_RX_DATX
DI3_TX_DAT
DI3_TX_DATX
DI3_SYS_CLK
DI3_SYS_CLK_EN
RESET_N
DI3_REF_CLK_EN
TP401 TP402
TP403 TP404
IPC_I2S_CLK
TP405
IPC_I2S_DIN
TP408
IPC_I2S_DOUT
VSD2_1.8V
TP409
IPC_I2S_SYNC
CP_CRASH_INT
TP412
M9
IPC_SRDY
EINT1
M8
EINT2 IPC_MRDY
K10
EINT3 OMAP_SEND
N10
I2C1_SCL
P9
I2C1_SDA
B6
DSP_AUDIO_IN1 DSP_AUDIO_IN1
N8
CLKOUT0
P10
CLKOUT2
N4
T_OUT0 MODEM_SEND
P3
T_OUT1 GSM_TXON_IND
R5
RESET2_N
N13
MIPI_HSI_RX_DATA
M14
MIPI_HSI_RX_FLG
L13
MIPI_HSI_RX_RDY
P13
MIPI_HSI_RX_WAKE MIPI_HSI_AC_WAKE
N12
MIPI_HSI_TX_DATA MIPI_HSI_CA_DATA
L11
MIPI_HSI_TX_FLG MIPI_HSI_CA_FLAG
M15
MIPI_HSI_TX_RDY MIPI_HSI_AC_READY
M13
MIPI_HSI_TX_WAKE MIPI_HSI_CA_WAKE
A13
MEM_A_0 MEM_A[0]
A11
MEM_A_1 MEM_A[1]
A10
MEM_A_2 MEM_A[2]
A9
MEM_A_3 MEM_A[3]
A8
MEM_A_4 MEM_A[4]
C12
MEM_A_5 MEM_A[5]
B9
MEM_A[6]
MEM_A_6
U402
C9
MEM_A_7 MEM_A[7]
A16
MEM_A_8 MEM_A[8]
B17
MEM_A_9 MEM_A[9]
C17
MEM_A_10 MEM_A[10]
D17
MEM_A_11 MEM_A[11]
E17
MEM_A_12 MEM_A[12]
F17
MEM_A_13 MEM_A[13]
G17
MEM_A_14 MEM_A[14]
H17
MEM_A[15]
MEM_A_15
J16
MEM_A_16
H16
MEM_A_17
J15
MEM_A_18
G15
MEM_A_19
E16
MEM_A_20
D16
MEM_A_21
C16
MEM_A_22
B16
MEM_A_23
H11
MEM_AD[0]
MEM_AD_0
G11
MEM_AD_1 MEM_AD[1]
G9
MEM_AD_2 MEM_AD[2]
D8
MEM_AD_3 MEM_AD[3]
F9
MEM_AD_4 MEM_AD[4]
E8
MEM_AD_5 MEM_AD[5]
E9
MEM_AD_6 MEM_AD[6]
D10
MEM_AD_7 MEM_AD[7]
E11
MEM_AD_8 MEM_AD[8]
A7
MEM_AD[9]
MEM_AD_9
H10
MEM_AD_10 MEM_AD[10]
D11
MEM_AD_11 MEM_AD[11]
D12
MEM_AD_12 MEM_AD[12]
D13
MEM_AD_13 MEM_AD[13]
J12
MEM_AD_14 MEM_AD[14]
F13
MEM_AD_15 MEM_AD[15]
- 171 -
NAND MCP
VSD2_1.8V
U401
A8
VDD1
C1
VDD2
G1
C401 C402 C403 C404 C405 VDD3
G10
2.2u VDD5
0.1u 0.1u 0.1u 0.1u
L1
VDD4
N8
VDD6
B9
VDDQ1
C10
VDDQ6
D9
VDDQ5
E10
VDDQ4
F9
VDDQ10
H10
VDDQ9
J9
VDDQ2
K9
VDDQ8
L10
VDDQ7
M9
VDDQ3
A2
NC27
D4
NC20
D6
NC21
E3
NC9
E4
NC19
E5
NC8
E7
NC11
E8
NC12
F1
NC17
F3
NC18
F4
NC7
F5
NC16
F6
NC25
F7
NC6
G3
NC10
G4
NC5
G5
NC13
G6
NC14
G7
NC4
H4
NC2
H5
MIPI_HSI_AC_DATA|McSPI4_SIMO NC24
H6
NC22
MIPI_HSI_AC_DATA J6
NC23
MIPI_HSI_AC_FLAG|McSPI4_SOMI L3
NC15
L4
NC3
MIPI_HSI_AC_FLAG
VSD2_1.8V
McSPI4_SIMO
McSPI4_SOMI
McSPI4_CLK A5
VCC1
M5
MIPI_HSI_CA_READY|McSPI4_CLK
VCC2
C420 C421 C422
MIPI_HSI_CA_READY
2.2u
0.1u 0.1u
A9
VSS1
B1
VSS4
B5
VSS8
B10
VSSQ5
C9
VSSQ4
D10
VSSQ9
E9
VSSQ8
F10
VSSQ3
G9
VSS2
H1
VSS3
H9
VSSQ10
J10
VSSQ1
K10
VSSQ2
L2
VSS5
L9
VSSQ6
M10
VSSQ7
N6
VSS6
N9
VSS7
USB_VBUS
IFX_USB_VBUS
R415
100K
Q401
1 6
S1 D1
UART_RX_SW
2 5
IFX_USB_VBUS_EN G1 G2
(Active high)
3 4
D2 S2
R416
4.7K
Copyright © 2011 LG Electronics. Inc. All right reserved.
7. CIRCUIT DIAGRAM
J4
A0 MEM_AD[0]
K1
A1 MEM_AD[1]
K2
A2 MEM_AD[2]
K3
A3 MEM_AD[3]
B2
A4
MEM_AD[4]
C2
A5 MEM_AD[5]
D1
A6 MEM_AD[6]
C3
A7 MEM_AD[7]
D2
A8 MEM_AD[8]
C4
A9 MEM_AD[9]
J3
A10 MEM_AD[10]
E2
A11 MEM_AD[11]
E1
A12 MEM_AD[12]
H3
BA0
MEM_AD[14]
J2
BA1 MEM_AD[15]
K4
DQ0 MEM_A[0]
K5
DQ1 MEM_A[1]
K6
DQ2 MEM_A[2]
K7
DQ3 MEM_A[3]
J8
DQ4 MEM_A[4]
K8
DQ5 MEM_A[5]
J7
DQ6
MEM_A[6]
J5
DQ7 MEM_A[7]
E6
DQ8 MEM_A[8]
C5
DQ9 MEM_A[9]
D8
DQ10 MEM_A[10]
C6
DQ11 MEM_A[11]
C8
DQ12 MEM_A[12]
C7
DQ13 MEM_A[13]
B8
DQ14 MEM_A[14]
B7
DQ15 MEM_A[15]
G8
/CK MEM_BFCLKO
F8
CK MEM_SDCLKO
D3
CKE DDR_CKE
H2
/CS MEM_CS1_N
F2
/RAS DDR_RAS_N
G2
/CAS DDR_CAS_N
J1
/WED MEM_WR_N
D7
UDQM MEM_BC1_N
H8
LDQM MEM_BC0_N
D5
UDQS DDR_DQS[1]
H7
LDQS DDR_DQS[0]
M1
IO0
MEM_AD[0]
M2
IO1 MEM_AD[1]
M3
IO2 MEM_AD[2]
L5
IO3 MEM_AD[3]
N7
IO4 MEM_AD[4]
L6
IO5 MEM_AD[5]
M6
IO6 MEM_AD[6]
L8
IO7 MEM_AD[7]
N2
IO8
MEM_AD[8]
N3
IO9
MEM_AD[9]
M4
IO10
MEM_AD[10]
N4
IO11
MEM_AD[11]
N5
IO12
MEM_AD[12]
M7
IO13
MEM_AD[13]
L7
IO14
MEM_AD[14]
M8
IO15
MEM_AD[15]
A6
/CE MEM_CS0_N
A3
/RE
MEM_RD_N
A7
/WE MEM_WR_N
A4
CLE MEM_WAIT_N
B4
ALE MEM_ADV_N
B3
/WP MEM_WP
B6
R/B MEM_BUSY/
Analog switch for USIF1
USIF1_SW
VBAT U403
1 7 UART1_RX_IPC
VCC 2B0
2 6
1B1 GND
C442
100n
Only for training and service purposes