Supermicro 440LX Reference Manual
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Supermicro 440LX Reference Manual

Supermicro 440LX Reference Manual

Supermicro 440lx motherboards: reference guide
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S
UPER
®
440LX Chipset

AMI BIOS

REFERENCE MANUAL
Revision 1.1

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  • Page 1: Ami Bios

    UPER ® 440LX Chipset AMI BIOS REFERENCE MANUAL Revision 1.1...
  • Page 2 LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF THE REPAIRING, REPLACING, OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA. Copyright © 1998 by SUPERMICRO COMPUTER INC. All rights reserved. Printed in the United States of America.

  • Page 3: Table Of Contents

    BIOS User's Manual Table of Contents Chapter 1: AMI BIOS 1-1 Introduction System BIOS ... 1-1 Configuration Data ... 1-1 How Data Is Configured ... 1-1 POST Memory Test ... 1-1 1-2 BIOS Features ... 1-2 BIOS Configuration Summary Screen ... 1-3 AMIBIOS Setup ...
  • Page 4 Table of Contents Appendix A: BIOS Error Beep Codes ... A-1 Appendix B: AMI BIOS POST Diagnostic Error Messages ... B-1...
  • Page 5 PRINTED IN U.S.A.

  • Page 6: Chapter 1: Ami Bios

    Chapter 1: AMI BIOS Chapter 1 AMI BIOS 1-1 Introduction This chapter describes the AMIBIOS for the Intel 440FX/440LX ® chipset which is designed for Intel Pentium Pro 150/166/180/200 MHz and Pentium II 233/266/300 MHz processors. The AMI ROM BIOS is stored in the Flash EEPROM and is easily upgraded using a floppy disk-based program.

  • Page 7: Bios Features

    BIOS User's Manual Made in U.S.A. Mainboard Rev 1.3 BIOS Release 120497 xxxxx KB OK Hit <DEL> if you want to run SETUP (C) American Megatrends Inc., XX-XXXX-XXXXXX-XXXXXXXX-XXXXXX-XXXX-X 1-2 BIOS Features • supports Plug and Play V1.0A and DMI 2.0 •...

  • Page 8: Bios Configuration Summary Screen

    • chassis intrusion detector input • watchdog comparison of all monitored values • POST code storage RAM • ISA and I C serial bus interfaces • up to five positive voltage inputs • up to two negative voltage inputs • up to three fan speed monitoring inputs BIOS Configuration Summary Screen AMIBIOS displays a screen that looks similar to the following...
  • Page 9 BIOS User's Manual Figure 1-1. Standard Option Highlighted Figure 1-2. Settings for Standard Option...

  • Page 10: Chapter 2: Running Setup

    Chapter 2: Running Setup Chapter 2 Running Setup* *Optimal and Fail-Safe default settings are bolded in text unless otherwise noted. The WinBIOS Setup options described in this section are selected by choosing the appropriate high-level icon from the Standard Setup screen.
  • Page 11 BIOS User's Manual AMI BIOS Hard Disk Drive Types Type Cylinders Heads Precompensation 1024 1024 1024 1024 1024 1024 1224 ENTER PARAMETERS PROVIDED WITH HARD DRIVE Write Landing Sectors Zone 65535 65535 65535 65535 65535 65535 65535 65535 1023 65535 65535 65535 65535...
  • Page 12 Entering Drive Parameters You can also enter the hard disk drive parameters. The drive parameters are: Parameter Description Type The number for a drive with certain identification parameters. Cylinders The number of cylinders in the disk drive. Heads The number of heads. Write The size of a sector gets progressively smaller as the track Precompensation...

  • Page 13: Advanced Setup

    BIOS User's Manual 2-1-2 Advanced Setup Quick Boot Set this option to Enabled to permit AMIBIOS to boot within 5 seconds. The Settings are Disabled or Enabled. Pri Master ARMD Emulated as Pri Slave ARMD Emulated as Sec Master ARMD Emulated as Sec Slave ARMD Emulated as Options for Pri Master ARMD Emulated as, Pri Slave ARMD Emulated as, Sec Master ARMD Emulated as and Sec Slave...
  • Page 14 Chapter 2: Running Setup The BIOS will attempt to read the boot record from 1st, 2nd, 3rd and 4th boot device in the selected order until it is successful in reading the booting record. The BIOS will not attempt to boot from any device which is not selected as the boot device.
  • Page 15 BIOS User's Manual by predicting future device failures. The hard disk needs to be S.M.A.R.T. capable. The settings for this option are Disabled or Enabled. *Note: SMART cannot predict all future device failures. SMART should be used as a warning tool, not as a tool to predict the device reliability.

  • Page 16: Chipset Setup

    Chapter 2: Running Setup System Bios Cacheable AMIBIOS always copies the system BIOS from ROM to RAM for faster execution. The settings are Disabled or Enabled. Note: the Fail-Safe default setting is Disabled. Set this option to Enabled to permit the contents of F0000h RAM memory segment to be written to and read from cache memory.
  • Page 17 BIOS User's Manual SDRAM Autosizing Support If the Serial Presence Detect (SPD) is not available, then the BIOS will try to detect the memory and do the autosizing. The settings for this option are Auto, Enabled or Disabled. EDO DRAM Speed (ns) This option should be set according to the speed of the EDO DRAM in the system.
  • Page 18 Chapter 2: Running Setup SDRAM Timing Latency Use this feature to select the SDRAM timing delay. The settings for this option are Manual or Auto. SDRAM RAS to CAS The settings for this option are 3 Clks or 2 Clks. SDRAM CAS Lat This feature is for the Column Address Strobe latency.
  • Page 19 BIOS User's Manual Type F DMA Buffer Control 1 Type F DMA Buffer Control 2 Instead of 8 sysclock, Type F DMA only requires 3 sysclock to finish the data transfer. These two options are device dependent. The settings are Channel 0, Channel 1, Channel 2, Disabled, Channel 3, Channel 5, Channel 6 or Channel 7.
  • Page 20 Chapter 2: Running Setup MAA 13.2 Bufl Strength RCSA1/RCSB1 Buf. Strength RCSA2/RCSB2 Buf. Strength RCSA3/RCSB3 Buf. Strength RCSA4/RCSB4 Buf. Strength CDQB 5,1 Buf. Strength CDQA 5,1 Buf. Strength CDQA 0, 2:4, 6:7 Buf. Strength RCSA5/RCSB5 Buf. Strength RCSA6/RCSB6 Buf. Strength RCSA7/RCSB7 Buf.
  • Page 21 BIOS User's Manual PIIX4 SERR# Use this feature for the SERR# generation due to delayed trans- action time-out enable. The settings are: Disabled or Enabled. USB Passive Release Enable The settings for this option are: Disabled or Enabled. When set to Enabled, it allows the PIIX4 to use Passive Release while transferring control information or data for USB transactions.

  • Page 22: Power Management

    Chapter 2: Running Setup 2-1-4 Power Management ACPI Aware OS Use this feature if your operating system supports Microsoft's Advanced Configuration and Power Interface (ACPI) standard. The settings are: Yes or No. Power Management/APM This power conservation feature is specified by Intel and Microsoft INT 15h Advance Power Management BIOS functions.
  • Page 23 BIOS User's Manual Hard Disk Timeout (Minute) This option specifies the length of a period of hard disk drive inactivity. When this length of time expires, the computer enters power-conserving state specified in the Hard Disk Power Down Mode option. The settings are Disabled and 1 Min through 15 Min in 1 minute intervals.

  • Page 24: Pci/Pnp Setup

    Chapter 2: Running Setup Device 3 (Secondary Slave IDE) These options are for event monitoring. The settings for each of these options are Monitor or Ignore. LAN Wake-Up RTC Wake-UP Hour Minute Options for LAN Wake-Up and RTC Wake-Up are Disabled and Enabled.
  • Page 25 BIOS User's Manual ters of both devices to be identical. This option must be set to Enabled if any ISA adapter card installed in the system requires VGA palette snooping. PCI IDE Busmaster The settings are: Disabled or Enabled. Offboard PCI IDE Card This option specifies if an offboard PCI IDE controller adapter card is installed in the computer.
  • Page 26 Chapter 2: Running Setup DMA Channel 0 DMA Channel 1 DMA Channel 3 DMA Channel 5 DMA Channel 6 DMA Channel 7 These DMA channels control the data transfers between the I/O devices and the system memory. The chipset allows the BIOS to choose which channels to do the job.

  • Page 27: Peripheral Setup

    BIOS User's Manual Reserved Memory Address This option specifies the beginning address (in hex) of the reserved memory area. The specified ROM memory area is reserved for use by legacy ISA adapter cards. The settings are C0000, C4000, C8000, CC000, D0000, D4000, D8000, or DC000. 2-1-6 Peripheral Setup OnBoard FDC This option enables the FDC (Floppy Drive Controller) on the...
  • Page 28 Chapter 2: Running Setup Parallel Port Mode This option specifies the parallel port mode. The settings are Normal, Bi-Dir, EPP or ECP. When set to Normal, the normal parallel port mode is used. Use Bi-Dir to support bidirectional transfers. Use EPP (Enhanced Parallel Port) to provide asymmet- ric bidirectional data transfer driven by the host device.

  • Page 29: Security Setup

    The above features are for the onboard National Semiconductor's LM 78 System Hardware Monitor used for PC health monitoring. The motherboards with LM 78 have seven onboard voltage monitors for the CPU core, CPU I/O, +3.3V, +5V, -5V, +12V, and - 12V, and three fan status monitors.

  • Page 30: Anti-Virus

    The password check option is enabled in the Advanced Setup by choosing either Always or Setup. CMOS RAM. You can enter a password by typing the password on the keyboard, selecting each letter via the mouse, or selecting each letter via the pen stylus. for each specific hardware platform.

  • Page 31: Optimal Default

    BIOS User's Manual 2-4-1 Optimal Default The Optimal default settings provide optimum performance settings for all devices and system features. 2-4-2 Fail-Safe Default The Fail-Safe default settings consist of the safest set of param- eters. Use them if the system is behaving erratically. should always work but do not provide optimal system perfor- mance characteristics.

  • Page 32: Appendix A: Bios Error Beep Codes

    Appendix A: BIOS Error Beep Codes Appendix A BIOS Error Beep Codes During the POST (Power-On Self-Test) routines, which are per- formed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process.
  • Page 33 BIOS User’s Manual Beeps Error message Refresh Failure Parity Error Base 64 KB Memory Failure Timer Not Operational Processor Error 8042 - Gate A20 Failure Processor Exception Interrupt Error Display Memory Read/Write Error ROM Checksum Error CMOS Shutdown Register Read/Write Error Cache memory bad - do not enable cache Refer to the table on page A-3 for solutions to the error beep...
  • Page 34 Appendix A: BIOS Error Beep Codes If it beeps... 1, 2, 3 times reseat the memory SIMMs or DIPs. system still beeps, replace the memory. 6 times reseat the keyboard controller chip. still beeps, replace the keyboard controller. different keyboard, or replace the keyboard fuse, if the keyboard has one.
  • Page 35 BIOS User’s Manual...

  • Page 36: Appendix B: Ami Bios Post Diagnostic Error Messages

    Appendix B: AMI BIOS POST Diagnostics Error Messages Appendix B AMI BIOS POST Diagnostic Error Messages This section describes the power-on self-tests (POST) port 80 codes for the AMI BIOS. Check Point Description NMI is Disabled. Next, checking for a soft reset or a power-on condition.
  • Page 37 BIOS User’s Manual Check Point Description Next, checking if the <End or <Ins> keys were pressed during power on. Initialize CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the <End> key was pressed. Next, disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2.
  • Page 38 Appendix B: AMI BIOS POST Diagnostics Error Messages Check Point Description Bus initialization system, static, output devices will be done next, if present. Passing control to the video ROM to perform any required configuration before the video ROM test. All necessary processing before passing control to the video ROM is done.
  • Page 39 BIOS User’s Manual Check Point Description The new cursor position has been read and saved. Displaying the Hit <DEL> message next. Preparing the descriptor tables next. The descriptor tables are prepared. mode for the memory test next. Entered protected mode. diagnostics mode next.
  • Page 40 Appendix B: AMI BIOS POST Diagnostics Error Messages Check Point Description The memory above 1 MB has been cleared via a soft reset. Saving the memory size next. Going to checkpoint 52h next. The memory test started, but not as the result of a soft reset.
  • Page 41 BIOS User’s Manual Check Point Description The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next. The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next. Completed programming DMA controllers 1 and 2. Initializing the 8259 interrupt controller next.
  • Page 42 Appendix B: AMI BIOS POST Diagnostics Error Messages Check Point Description Returned from WINBIOS Setup and cleared the screen. Performing any necessary programming after WINBIOS Setup next. The programming after WINBIOS Setup has been completed. Displaying the power-on screen message next.
  • Page 43 BIOS User’s Manual Check Point Description Set the timer and printer base addresses. RS-232 base address next. Returned after setting the RS-232 base address. Performing Coprocessor test next. Required initialization before the Coprocessor test is over. Initializing the Coprocessor next. Coprocessor initialized.
  • Page 44 Appendix B: AMI BIOS POST Diagnostics Error Messages Check Point Description Initialization after E000 option ROM control has completed. Displaying the system configuration next. Building the multiprocessor table, if necessary. POST next. The system configuration is displayed. Uncompressing the DMI data and initializing DMI. Copying any code to specific areas.
  • Page 45 BIOS User’s Manual B-10...

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