Overview Of Reconfigurable I/O; Reconfigurable I/O Concept - National Instruments Multifunction RIO NI R Series User Manual

Caution
Damage can result if the J2 lines are driven by the sub-bus.
NI PXI-78xxR Signal
PXI_Trig<0..7>
PXI_Clk10
PXI_Star
*
PXI_Lbl<0..12>
*
PXI_Lbr<0..12>
*
NI PXI-781xR/783xR only

Overview of Reconfigurable I/O

Reconfigurable I/O Concept

© National Instruments Corporation
PXI-specific features are implemented on the J2 connector of the
CompactPCI bus. Table 1-2 lists the J2 pins used by the NI PXI-78xxR.
The NI 78xxR is compatible with any CompactPCI chassis with a sub-bus
that does not drive these lines. Even if the sub-bus is capable of driving
these lines, the R Series device is still compatible as long as those pins on
the sub-bus are disabled by default and are never enabled.
Table 1-2. Pins Used by the NI PXI-78 xx R
PXI Pin Name
PXI Trigger<0..7>
PXI Clock 10 MHz
PXI Star Trigger
LBL<0..12>
LBR<0..12>
This section explains reconfigurable I/O and describes how to use the
LabVIEW FPGA Module to build high-level functions in hardware.
Refer to Chapter 2, Hardware Overview of the NI
of the I/O resources on the NI 78xxR.
R Series Multifunction RIO devices are based on a reconfigurable FPGA
core surrounded by fixed I/O resources for analog and digital input and
output. You can configure the behavior of the reconfigurable FPGA to
match the requirements of the measurement and control system. You can
implement this user-defined behavior as an FPGA VI to create an
application-specific I/O device.
PXI J2 Pin Number
A16, A17, A18, B16, B18, C18, E16, E18
E17
D17
A1, A19, C1, C19, C20, D1, D2, D15, D19,
E1, E2, E19, E20
A2, A3, A20, A21, B2, B20, C3, C21,
D3, D21, E3, E15, E21
1-3 R Series Multifunction RIO User Manual
Chapter 1 Introduction
78xxR, for descriptions