The Pcie Tab - Intel Arria 10 FPGA User Manual

4.4.6. The PCIe Tab

This tab allows you to run a PCIe loopback test on your board. You can also load the
design and use an oscilloscope to measure an eye diagram of the PCIe transmit
signals.
Figure 21. The PCIe Tab
Control
Status
® ®
Intel Arria 10 FPGA Development Kit User Guide
34
Displays the following status information during a loopback test:
PLL lock—Shows the PLL locked or unlocked state.
Pattern sync—Shows the pattern synced or not synced state. The pattern
is considered synced when the start of the data sequence is detected.
4. Board Test System
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Description
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