Table of Contents
Advertisement
Quick Links
www.ti.com
User's Guide
TPS650350-Q1 EVM User's Guide
The TPS650350-Q1 EVM is an evaluation board for the TPS65035x-Q1 Power Management Integrated Circuits
(PMICs). The EVM includes an onboard USB-to-I
inputs and outputs, and test points for common measurements.
1
Introduction.............................................................................................................................................................................3
2
Requirements..........................................................................................................................................................................3
3 Operation Instructions...........................................................................................................................................................
Configurations................................................................................................................................................................6
Points...............................................................................................................................................................................7
6 Graphical User Interface........................................................................................................................................................
7 Typical Performance Plots...................................................................................................................................................
8 TPS650350-Q1 EVM Schematic...........................................................................................................................................
10 TPS650350-Q1 EVM Bill of Materials................................................................................................................................
Figure 4-1. TPS650350-Q1 EVM Top View.................................................................................................................................
Figure 5-1. TPS650350-Q1 EVM Test Point Locations...............................................................................................................
Figure 6-6. Register Page
Figure 6-11. Sequencing Overview Including GPIO..................................................................................................................
Figure 6-13. TPS6503xx-Q1 GUI Re-Program PMIC Page......................................................................................................
Figure 7-1. TPS650350-Q1 Default Power Up Sequence.........................................................................................................
Figure 7-2. TPS650350-Q1 Default Power Down Sequence....................................................................................................
Transient.............................................................................................................................................19
Transient.............................................................................................................................................19
Transient.............................................................................................................................................20
Figure 7-6. LDO Load Transient................................................................................................................................................
Figure 7-7. Buck 1 Output Voltage Ripple.................................................................................................................................
Figure 7-8. Buck 2 Output Voltage Ripple.................................................................................................................................
Figure 7-9. Buck 3 Output Voltage Ripple.................................................................................................................................
Figure 7-10. LDO Output Noise Density....................................................................................................................................
Figure 8-2. MSP432E401Y Schematic......................................................................................................................................
Layer.................................................................................................................................................................24
Figure 9-2. Mid-Layer 1.............................................................................................................................................................
Figure 9-3. Mid-Layer 2.............................................................................................................................................................
Figure 9-4. Mid-Layer 3.............................................................................................................................................................
Figure 9-5. Mid-Layer 4.............................................................................................................................................................
SLVUCG6 - NOVEMBER 2022
Submit Document Feedback
ABSTRACT
2
C adapter, power terminals and jumpers for all DC regulator
Table of Contents
Layers.........................................................................................................................................24
List of Figures
Chart............................................................................................................9
Options....................................................................................................................................10
Port......................................................................................................................................10
Screen..........................................................................................................................11
Page...............................................................................................................12
Page.....................................................................................................13
Settings.......................................................................................................14
Output.........................................................................................................................................14
Tab.....................................................................................................................................15
Diagram............................................................................................................................16
Script...............................................................................................................................18
Schematic......................................................................................................................................22
Copyright © 2022 Texas Instruments Incorporated
Table of Contents
TPS650350-Q1 EVM User's Guide
3
8
19
22
30
6
8
15
17
19
19
20
20
20
21
21
23
25
26
27
28
1
Advertisement
Table of Contents
Related Manuals for Texas Instruments TPS650350-Q1 EVM
Summary of Contents for Texas Instruments TPS650350-Q1 EVM
-
Page 1: Table Of Contents
User’s Guide TPS650350-Q1 EVM User's Guide ABSTRACT The TPS650350-Q1 EVM is an evaluation board for the TPS65035x-Q1 Power Management Integrated Circuits (PMICs). The EVM includes an onboard USB-to-I C adapter, power terminals and jumpers for all DC regulator inputs and outputs, and test points for common measurements. - Page 2 Table 3-13. VIO Power Source (J6)............................. Table 3-14. I2C Pull-up Source (J6).............................6 Table 5-1. TPS650350-Q1 EVM Test Points..........................7 Table 6-1. Functionally Equivalent Generic Part Numbers......................Table 10-1. TPS650350-Q1 EVM Bill of Materials........................30 Trademarks Google Chrome ™ is a trademark of Google, LLC.
-
Page 3: Introduction
USB adapter to PMIC functional pins. These can be disconnected for flexibility. Table 3-3. Adapter PMIC Connections Jumper PMIC Pin nINT SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 4: Table 3-4. Buck 1 Power Source (J3)
GPIO 3.2 Regulator Input Supplies and Features The four regulators on the TPS650350-Q1 EVM can be supplied with multiple supplies. The following tables show the possible supply configurations in addition to key specifications and programmable features for each regulator. -
Page 5: Table 3-9. Low-Vin (Buck2 And Buck3) Features
Pin 7 (PMIC LDO Output Rail) Pin 8 (VIO Input Supply Rail) Pin 9 (Dedicated 3.3 V LDO) Pin 10 (VIO Input Supply Rail) SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 6: Evm Configurations
Pin 11 (I2C Pull-up Rail) Pin 11 (I2C Pull-up Rail) 4 EVM Configurations The following sections outline how to configure the TPS650350-Q1 EVM for general experimentation. Figure 4-1. TPS650350-Q1 EVM Top View TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright ©... -
Page 7: Test Points
Test Points 5 Test Points 5.1 Voltage Test Points The TPS650350-Q1 EVM contains 29 test points for various measurements. Trace assignments to the test points are shown in Table 5-1. For reference, Figure 5-1 demonstrates the test point locations on the EVM. -
Page 8: Graphical User Interface
, macOS ® , or Linux ® 6.1 TPS650350-Q1 EVM Debugging Refer to Figure 6-1 to debug potential issues while using the TPS650350-Q1 EVM. TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 9: Figure 6-1. Tps650350-Q1 Evm Debugging Flow
© Check VSYS and VIO. to device? Ensure I2C jumper is populated at J6 Debug Complete Figure 6-1. TPS650350-Q1 EVM Debugging Flow Chart SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 10: Figure 6-2. Opening Serial Port Options
The GUI contains the following five sections, selectable on the left side of the GUI or by clicking the Menu tab in the top left corner. • Home • Block Diagram TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 11: Figure 6-4. Tps6503Xx-Q1 Gui Home Screen
The Block Diagram section displays the typical components and functional blocks of the PMIC. A block diagram for the Programming BoosterPack is also shown. SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 12: Figure 6-5. Tps6503Xx-Q1 Gui Block Diagram Page
A drop-down menu selection at the top right of the register map indicates how the registers are written as the user interacts with the register page. With Immediate selected, any update to the register page is automatically TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 13: Figure 6-7. Tps6503Xx-Q1 Gui Device Configuration Page
PMIC. This drop down box is not adjustable if a device is connected to the GUI. SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 14: Figure 6-8. Device Selection For Generating Nvm Settings
3. Click File > Save Settings in the top left corner of the GUI to export the register settings in a JSON file. Provide the JSON file to TI to generate the NVM spin. Figure 6-9. Example Settings Output TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 15: Figure 6-10. Sequencing Overview Tab
Sequencing Overview tab. Note that when using GPIO for sequencing, the GPIO Function must be Enabled. Figure 6-11. Sequencing Overview Including GPIO SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 16: Figure 6-12. Gui Generated Timing Diagram
After the EEPROM Program Command is sent, the device stores the existing register configurations permanently, and the PMIC automatically restarts with the latest settings. The device can be re-programmed multiple times to evaluate various configurations. TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 17: Figure 6-13. Tps6503Xx-Q1 Gui Re-Program Pmic Page
Graphical User Interface Figure 6-13. TPS6503xx-Q1 GUI Re-Program PMIC Page SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 18: Figure 6-14. Gui Configuration Crc Script
Configuring the Power Sequence. 2. Once settings are verified and validated, configure the TPS650350-Q1 EVM for a typical camera application: a. Ensure the I2C pull-up jumper is populated at J6. b. Supply the PMIC VIO with either the Buck 1 or Buck 2 output. See Selecting the Logic Supply Voltage. -
Page 19: Typical Performance Plots
IOUT = 1 mA to 600 mA in 1 µs µs Figure 7-3. Buck 1 Load Transient Figure 7-4. Buck 2 Load Transient SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 20: Figure 7-5. Buck 3 Load Transient
VIN =3.3 V VOUT = 1.8 V IOUT = 600 mA Figure 7-7. Buck 1 Output Voltage Ripple Figure 7-8. Buck 2 Output Voltage Ripple TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 21: Figure 7-9. Buck 3 Output Voltage Ripple
Figure 7-9. Buck 3 Output Voltage Ripple 7.4 LDO Output Noise VIN = 3.3 V VOUT = 2.8 V IOUT = 300 mA Figure 7-10. LDO Output Noise Density SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 22: Tps650350-Q1 Evm Schematic
TPS650350-Q1 EVM Schematic www.ti.com 8 TPS650350-Q1 EVM Schematic Figure 8-1. TPS650350-Q1 Schematic TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 23: Figure 8-2. Msp432E401Y Schematic
TPS650350-Q1 EVM Schematic Figure 8-2. MSP432E401Y Schematic SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 24: Tps650350-Q1 Evm Pcb Layers
TPS650350-Q1 EVM PCB Layers www.ti.com 9 TPS650350-Q1 EVM PCB Layers Figure 9-1. Top Layer TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 25: Figure 9-2. Mid-Layer 1
TPS650350-Q1 EVM PCB Layers Figure 9-2. Mid-Layer 1 SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 26: Figure 9-3. Mid-Layer 2
TPS650350-Q1 EVM PCB Layers www.ti.com Figure 9-3. Mid-Layer 2 TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 27: Figure 9-4. Mid-Layer 3
TPS650350-Q1 EVM PCB Layers Figure 9-4. Mid-Layer 3 SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 28: Figure 9-5. Mid-Layer 4
TPS650350-Q1 EVM PCB Layers www.ti.com Figure 9-5. Mid-Layer 4 TPS650350-Q1 EVM User's Guide SLVUCG6 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 29: Figure 9-6. Bottom Layer (Mirrored)
TPS650350-Q1 EVM PCB Layers Figure 9-6. Bottom Layer (Mirrored) SLVUCG6 – NOVEMBER 2022 TPS650350-Q1 EVM User's Guide Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated... -
Page 30: Tps650350-Q1 Evm Bill Of Materials
TPS650350-Q1 EVM Bill of Materials www.ti.com 10 TPS650350-Q1 EVM Bill of Materials Table 10-1. TPS650350-Q1 EVM Bill of Materials Designator Quantity Value Description Package Reference Part Number Manufacturer !PCB1 Printed Circuit Board BMC101 C1, C2 10uF CAP, CERM, 10 µF, 25 V,+/- 5%, X7R, AEC-... - Page 31 TPS650350-Q1 EVM Bill of Materials Table 10-1. TPS650350-Q1 EVM Bill of Materials (continued) Designator Quantity Value Description Package Reference Part Number Manufacturer J1, J2, J7, J8, J9, Standard Banana Jack, Uninsulated, 8.9mm Keystone575-8 575-8 Keystone J10, J11, J12, J13,...
- Page 32 TPS650350-Q1 EVM Bill of Materials www.ti.com Table 10-1. TPS650350-Q1 EVM Bill of Materials (continued) Designator Quantity Value Description Package Reference Part Number Manufacturer R6, R14, R18 RES, 330, 5%, 0.063 W, AEC-Q200 Grade 0, CRCW0402330RJNED Vishay-Dale 0402 100k RES, 100 k, 5%, 0.1 W, AEC-Q200 Grade 0,...
- Page 33 TPS650350-Q1 EVM Bill of Materials Table 10-1. TPS650350-Q1 EVM Bill of Materials (continued) Designator Quantity Value Description Package Reference Part Number Manufacturer TP1, TP2, TP3, Test Point, Miniature, SMT Testpoint_Keystone_Miniature 5015 Keystone TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11,...
- Page 34 STANDARD TERMS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein.
- Page 35 www.ti.com Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product.
- Page 36 www.ti.com Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à...
- Page 37 www.ti.com EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices.
- Page 38 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated...
- Page 39 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated...