Philips 32PF9968/10 Service Manual page 136

EN 136 9. Q522.1E LA
9.6.12 Diagram B09B, STE100P (IC 7NA1)
Block Diagram
LEDS
LEDS
100Mb/s
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
RXD[3:0]
RX_ER
RX_DV
RX_CLK
HW
configuration
pins
HW Config
Power Down
Pin Configuration
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Circuit Descriptions, Abbreviation List, and IC Data Sheets
TX Channel
Parallel to
Scrambler
4B/5B
Serial
10Mb/s
NRZ To Manchester
Encoder
REGISTERS
RX Channel
100Mb/s
Descrambler
Serial to
4B/5B Code Align
Parallel
NRZ To Manchester
10Mb/s
Encoder
64 63 62 61 60 59 58 57 56
1
mf4
2
mf3
3
mf2
4
mf1
5
mf0
6
fde
7
gnda
8
nc
9
vcca
gnda 10
x2
11
12
x1
13
vcca
14
gnda
iref
15
vcca 16
17 18 19 20 21 22 23 24 25 26
Figure 9-18 Internal block diagram and pin configuration
NRZ To NRZI Binary To MLT3
Encoder
Encoder
Link Pulse
10 TX
Generator
Filter
Auto
Loopback
Negotiation
Binary To MLT3
Decoder
NRZI To NRZ
Clock Recovery
Decoder
10 TX Filter
Link Pulse
Detector
Clock Recovery
55 54 53 52 51 50 49
STE100P
27 28 29 30 31 32
TRANSMITTER
10/100
Clock
Generation
Adaptive
Equalization
BaseLine
Wander
RECEIVER
10/100
SMART
Squelch
48 rx_dv
47 rxd0
46 rxd1
45 vcce/i
44 rdx2
43 rdx3
42 mdc
41 mdio
40
gnde/i
39
vcce/i
38 ledr10
37
ledtr
36 ledl
35 ledc
34 leds
33 test_se
H_17650_081.eps
TXP
TXN
System
Clock
RXP
RXN
150108