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LC-46/60LE925E
Is the LVDS signal output from IC3302 (DIGITAL_AV_DECODER_&_MAIN_CPU_&_VIDEO PROCESSER) respectively?
LVDS0_D0N/P (D14/C14), LVDS0_D1N/P (D15/C15), LVDS0_D2N/P (D16/C16), LVDS0_CLKN/P_83MHz (D17/C17), LVDS0_D3N/P (D18/C18),
LVDS0_D4N/P (D19/C19), LVDS1_D0N/P (B14/A14), LVDS1_D1N/P (B15/A15), LVDS1_D2N/P (B16/A16), LVDS1_CLKN/P_83MHz (B17/A17),
LVDS1_D3N/P (B18/A18), LVDS1_D4N/P (B19/A19)
Is the LVDS signal input to IC2401.
LVDS0_D0N/P (A16/B16), LVDS0_D1N/P (A15/B15), LVDS0_D2N/P (A14/B14), LVDS0_CLKN/P_83MHz (A10/B10), LVDS0_D3N/P (B5/A5),
LVDS0_D4N/P (B4/A4), LVDS1_D0N/P (C2/C1), LVDS1_D1N/P (D2/D1), LVDS1_D2N/P (F2/F1), LVDS1_CLKN/P_83MHz (J2/J1), LVDS1_D3N/P
(L2/L1), LVDS1_D4N/P (P1/P2)
Is the LVDS signal input to IC2402.
FPGA_R10~19 (76~81, 84~87), FPGA_G10~19 (88~92, 95~99), FPGA_B10~19 (100~103, 106~108, 110~112), FPGA_R20~29 (115~124),
FPGA_G20~G29 (127~136), FPGA_B20~B29 (139~144, 1~2, 5~6), FPGA_H/VSYNC1 (7~8), FPGA_H/VSYNC2 (10~11), FPGA_DE1/DE2
(9, 12), FPGA_CLK1/2_74M (15~16), FPGA_CONT11/12 (17~18), FPGA_CONT11/22 (19~20)
Is the LVDS signal output from IC2402.
LVDS0_FPGA_D0N/P (71, 70), LVDS0_FPGA_D1N/P (69, 68), LVDS0_FPGA_D2N/P (65, 64), LVDS0_FPGA_CLKN/P_83MHz (63, 62),
LVDS0_FPGA_D3N/P (59, 58), LVDS0_FPGA_D4N/P (57, 56), LVDS1_FPGA_D0N/P (53, 52), LVDS1_FPGA_D1N/P (51, 50),
LVDS1_FPGA_D2N/P (47, 46), LVDS1_FPGA_CLKN/P_83MHz (45, 44), LVDS1_FPGA_D3N/P (41, 40), LVDS1_FPGA_D4N (39, 38)
Is the above-mentioned LVDS signal output to connector P2601?
Similarly, is LCD controller's control signal normal?
LCD Controller Unit:
Is the LVDS signal input to connector LW of LCD Controller Unit?
Check the panel module.
No picture on the display (1)
The picture doesn't appear in all modes.
YES
YES
YES
YES
YES
YES
YES
Check IC3302 and its peripheral control circuits.
(IC2002, IC3501, IC3502, X3302, etc.)
Check the line between IC3302 and IC2401.
Check the line between IC2401 and IC2402.
Check IC2402 and its peripheral control circuits.
NO
Check the line between IC2402 and P2601.
NO
Please check each control signal of DET_POW (DET_PNL12V),
PE (PNL_EN).
NO
NO Wire harness (LW) is checked.
7 – 8
NO
NO
NO
NO
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