Compaq EN Series Technical Reference Manual page 109

Chapter 5 Input/Output Interfaces
5.2.1.1 IDE Configuration Registers
The IDE controller is integrated into the south bridge (82371) component and configured as a
PCI device with bus mastering capability. The PCI configuration registers for the IDE controller
function (PCI device #20, function #1) are listed in Table 5-1.
Table 5–1. IDE PCI Configuration Registers
PCI
Conf.
Addr. Register
00-01h Vender ID
02-03h Device ID
04-05h PCI Command
06-07h PCI Status
08h Revision ID
09h Programming
0Ah Sub-Class
0Bh Base Class Code
0Dh Master Latency Timer
0Eh Header Type
0F-1Fh Reserved
20-23h BMIDE Base Address
NOTE:
Assume unmarked gaps are reserved and/or not used.
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the I/O mapped control registers
listed in Table 5-2.
Table 5–2. IDE Bus Master Control Registers
I/O Addr. Size
Offset (Bytes)
00h 2
02h 2
04h 4
08h 2
0Ah 2
0Ch 4
5-2 Compaq Deskpro EN Series of Personal Computers
Desktop and Minitower Form Factors
Table 5-1.
EIDE PCI Configuration Registers (82371 Function 1)
Table 5-2.
IDE Bus Master Control Registers
Register
Bus Master IDE Command (Primary)
Bus Master IDE Status (Primary)
Bus Master IDE Descriptor Ptr (Pri.)
Bus Master IDE Command (Secondary)
Bus Master IDE Status (Secondary)
Bus Master IDE Descriptor Ptr (Sec.)
Third Edition – September 1998
Value PCI
on Conf.
Reset Addr. Register
8086h 24-3Fh Reserved
7111h 40, 41h IDE Timing (Primary)
0000h 42, 43h IDE Timing (Secondary)
0000h 44h Slave IDE Timing
0Ah 45-47h Reserved
01h 48h UDMA Timing
01h 49h Reserved
80h 4A, 4Bh UDMA Timing
0000h 4C-F7h Reserved
80h F8-FBh Manufacturer's ID
00h FC-FFh Reserved
00h -- --
Default
Value
00h
00h
0000 0000h
00h
00h
0000 0000h
Value
on
Reset
--