Typical Uniprocessor Configuration; Typical Multiprocessor Configuration - Compaq EV68A Hardware Reference Manual

Figure 2–12 Typical Uniprocessor Configuration
L2 Cache
Tag
Store
Data
Store
Figure 2–13 shows a typical multiprocessor system, each processor with a second-level
cache. Each interface controller must employ a duplicate tag store to maintain cache
coherency. This system configuration could be used in a networked database server
application.
Figure 2–13 Typical Multiprocessor Configuration
L2
Cache
L2
Cache
21264/EV68A Hardware Reference Manual
21264
Tag
Address
Out
Address
Address
In
Data
Data
21264
Logic Chipset
21264
Host PCI
Bridge Chip
64-bit PCI Bus
Design Examples
21272 Core
Logic Chipset
Control
Chips
Data Slice
Chips
Host PCI
Bridge Chip
64-bit PCI Bus
21272 Core
Control
Chip
Data Slice
Chips
Host PCI
Bridge Chip
64-bit PCI Bus
Internal Architecture
Duplicate
Tag Store
(Optional)
DRAM
Arrays
Address
Data
FM-05573-EV67
DRAM
Arrays
Address
Data
DRAM
Arrays
Address
Data
FM-05574-EV67
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