Mbox Iprs; Dtb Tag Array Write Registers 0 And 1 - Dtb_Tag0, Dtb_Tag1; Dtb Tag Array Write Registers 0 And 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dtb Pte Array Write Registers 0 And; Performance Counter Control Register Input Select Fields - Compaq EV68A Hardware Reference Manual

Table 5–15 Performance Counter Control Register Fields Description (Continued)
Name
VAL
TAK
Table 5–16 Performance Counter Control Register Input Select Fields
SL0[4] SL1[3:2] Mode
0 00 Aggregate
0 01 Aggregate
0 10 Aggregate
0 11 Aggregate
1 00 ProfileMe
1 01 ProfileMe
1 10 ProfileMe
1 11 ProfileMe

5.3 Mbox IPRs

This section describes the internal processor registers that control Mbox functions.
5.3.1 DTB Tag Array Write Registers 0 and 1 – DTB_TAG0, DTB_TAG1
The DTB tag array write registers 0 and 1 (DTB_TAG0 and DTB_TAG1) are write-
only registers through which the two memory pipe DTB tag arrays are written. Write
transactions to DTB_TAG0 and DTB_TAG1 write data to registers outside the DTB
arrays. When write transactions to the corresponding DTB_PTE registers are retired,
the contents of both the DTB_TAG and DTB_PTE registers are written into their
respective DTB arrays, at locations determined by the round-robin allocation algorithm.
Figure 5–26 shows the DTB tag array write registers 0 and 1.
Figure 5–26 DTB Tag Array Write Registers 0 and 1
63 48 47
VA[47:13]
21264/EV68A Hardware Reference Manual
Extent Type Description
[1] RO Profiled instruction valid.
When set, indicates a nontrapping profiled instruction retired valid.
When clear, indicates that a nontrapping profiled instruction was
killed after the cycle in which it was mapped. Valid retire/abort status
for a trapping profiled instruction is determined by the trap type (see
I_STAT[TRAP_TYPE]).
[0] RO ProfileMe conditional branch taken.
Indicates program branch direction, if the profiled instruction is a
conditional branch.
PCTR0
Retired instructions
Cycle counting
Retired instructions
Cycle counting
Retired instructions
Cycle counting
Retired instructions
Cycle counting
PCTR1
Cycle counting
Not defined
Bcache miss or long latency probes
Mbox replay traps
Cycle counting
Inum retire delay
Bcache miss or long latency probes
Mbox replay traps
13 12
Internal Processor Registers
Mbox IPRs
0
LK99-0035A
5–25