North Star RAM-16-A Manual page 30

flop cannot be guaranteed to be met, and there is a small but
finite chance that it will go into a momentary indecisive
state. For this reason, a network of a resistor, capacitor,
Schmitt inverter, and Schmitt gate filter the output to avoid
the chance of sending an erroneous pulse down the delay
module. Since a Schottky flip-flop is used, the filter slows
down the signal by 10-15ns.
4. Whenever the processor resumes computation following a pause,
refresh cycles must be inhibited lest one collide with the
first memory cycle.
a. at the end of a wait state, the leading edge of PRDY or
XRDY sets the WAIT-EXIT flip-flop, inhibiting refresh
cycles. If this flip-flop initially comes up true, CLR
will reset it.
b. at the end of an 8080 halt phase (the Z80 maintains SMI
activity while halted) the trailing edge of SHLTA triggers
the HLT/RST-EXIT one-shot, inhibiting refresh cycles for a
few microseconds.
c. at the end of a system reset, the trailing edge of POC or
PRESET, if so jumpered,
the same one-shot.
BOARD SELECT AND CHIP SELECT
The RAM-16-A occupies two 8K regions of a 64K byte address space.
Address bits A15, A14, and A13 ct o to a one-of-eight decoder, the
outputs of which go to eight switches.
by fours, with 1, 3, 5, and 7 connected together as BS-CD/ and 2,
4, 6, and 8 connected together as BS-AB/.
configuration would be to have two adjacent switches ON and the
other six OFF. However, the two switches do not have to be
adjacent, as long as one is connected to BS-AB/ and one to BS-
CD/.
The board has four 4K regions corresponding to "lines" of chips
labeled A, B, C, and D (one hesitates to call them "rows" or
"columns" because that terminology is used to designate bit
arrays within the chips).
line should receive a RAS; other lines do a deselect
cycle. The line which is selected for a memory cycle is
determined by combining BS-AB and BS-CD with address bit A12,
while the RAS timing comes from the delay module.
that during a refresh cycle REF-SEL causes all four lines to
receive a RAS but not a CAS.
Memory cycles to all four lines on the board are inhibited if
OCCLUDE is true (see Bank Switching below), as none of the
outputs of the decoder can go low.
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The RAM-16-A recognizes three such cases:
(whichever occurs last) triggers
For a normal memory cycle, only one
Similarly, if the PH jumper
North Star 16K RAM BOARD
The switches are grouped
The most common
(CAS-only)
Note, however,