S3.2.2. Video/Audio Signal Process Block Diagram (2 - Panasonic HDC-SD100P Service Manual

S3.2.2. Video/Audio Signal Process Block Diagram (2)

IC601
(LCD COLOR DRIVER)
CLKIN
CLK27 SLLCD 11
T/C
IC3400
(VIDEO)
22 DATA0
BUS13 SLLCD0
RGB VIDEO
8BIT DAC
BUS13 SLLCD7
14 DATA7
9 RESET
VCOM
SCS
DRIVER
5 DAC
SERIAL
SDATA
6 CONTROL
SCLK
7
R-STRINGS
IC801
(EVF COLOR DRIVER)
CLKIN
CLK27 SLEVF
11
T/C
IC3400
(VIDEO)
22 DATA0
BUS13 SLEVF0
RGB VIDEO
8BIT DAC
BUS13 SLEVF7
14 DATA7
9 RESET
VCOM
SCS
DRIVER
5 DAC
SERIAL
SDATA
6
CONTROL
SCLK
7
R-STRINGS
IC3601
(VIDEO ENCODER)
27MHz or 74.25MHz
CKLIN Clock Gen
CLK74 V D 54
PLL
74.25MHz-> 148.5MHz
27MHz -> 54MHz 6.75/13.5/27/54/148.5MHz
YCbCr
DATA0 1
To IC3400
(VIDEO)
BUS37 YOD0
8 YCbCr to RGB
12
BUS37 YOD7
18-bit
RGB to YCbCr
BUS37 COD0
14
19
RGB
BUS37 COD7
DATA15 23
52
HDI
VDI 51
55 48 10 11 47
15
PVDD1 PVDD2 DVDD DVSS
CKV1
1
STV1
3
PCG1
55
CKH2
57
CKH1
58
STH1
60
ENB1
62
CL602
ROUT
LCD
27
CL601
GOUT
26
PW MBL5V
CL603
BOUT
25
PCD
D901~903
36
(BACK LIGHT)
COMH CL604
34
COMOUT
35
Q901~903
Q910
BLCONT1 44
PW EVFBL5V
CKV1
1
STV1
D801
3
PCG1
(BACK LIGHT)
55
CKH2
57
CKH1
58 Q801
STH1
60
ENB1
62
CL802
ROUT
EVF
27
CL801
GOUT
26
CL803
BOUT
25
PCD
36
COMH CL804
34
COMOUT
35
PDN SDA SCL SELA TMO
16 41
26 17 18
u-P I/F 50 TEST0
TEST
49 TEST1
Y Y
NTSC/PAL
Cb C
Composite Video
Cr Encoder CVBS HDYSDY
G
DAC1 36
Y/G Y/G
HDP SDC B
G
Cb/B Cb/B
DAC2 35
Component
Encoder
Cr/R Cr/R
HDPR
G
G G
DAC3 34
B B
Delay
R R
HDO S SDA VDAC
To IC3400
Delay Buffer 31
(VIDEO)
S CLK VDAC
VDO
Delay Buffer 30
VREF
33 32 37 39 38 29
AVDD AVSS VREF IREF BYPASS FLT
IC3701
(AVIO)
HDYIN/SDYIN
46
PbIN/CIN
44
CLAMP BUFFER
PrIN
48
LPF HPF HPF HPF
SDTI0
AODAT0 6
SDTO0
AIDAT0 17
BCLK0
CLK B0 2
To IC3400
LRCK0
(VIDEO)
CLK LR0 4
BCLK1
CLK B1 5
LRCK1
CLK LR1 3
AUDIO
CLK12 M I/F
CONT- LPF HPF HPF HPF
ROLLER
MCKI LPF HPF HPF HPF
8 PLL
To IC3400
AVIO RST
DE-
DAC
EMP
95 PDN
CDTI/SDA
20
CCLK/SCL CONTROL
22 REGISTER
I/F
CSN/CAD0
21
S-5
LINE1
"LINE1" HD-DC 54
LINE2
"LINE2" HD-DC 57
LINE3
"LINE3" HD-DC 60
To IC3400
HD YLEVEL
HDYOUT
56
HDYSAG
55
LPF
PbOUT
GCA
(SD) 58
PbSAG
59
PrOUT
50
PrSAG
51
VOUT
42
VSAG
41
IC4803
(MIC AMP)
INT0L
89 7
EXT0L
IPGA
81
(ALC)
IC4801
ADC0
LINE0L
(MIC AMP)
88
INT0R
90 7
EXT0R
93
IC4802
LINE0R
(MIC AMP)
91
INT1L
7
77
LINE1L
IPGA
76
(ALC)
IC4803
ADC1
(MIC AMP)
INT1R
78 1
LINE1R
79 IC4802
(MIC AMP)
INT2L
70 1
LINE2L
IPGA
69
(ALC)
ADC3
INT0L2
87
LIN0R2
92
LOUT
VOL 65
ROUT
VOL 66
OPGA
SPP
24
MIX
SPN
23
HDC-SD100 VIDEO/AUDIO SIGNAL PROCESS(2) CIRCUIT BLOCK DIAGRAM
JK6101
(D JACK)
1 LINE1
2 PBOUT
3 LINE2
HDYOUT
5
6 LINE3
To IC2006 9 D PLUG DET
10 PROUT
JK6102
(AV MULTI JACK)
1 G RGND
4 G VHPR
5 G LHPL
To IC2006 6 PLUGIN L
6
6
FP4801
(To ECM)
6 2 ECM[F]
3 ECM[R]
4 ECM[B]
5 ECM[C]
2
7 ECM[L]
2
SPEAKER