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Interrupt check in port group unit
When interrupts are enabled in two or more port groups, check the PPORTINTFGRP.PxINT bit in the interrupt
handler first. It helps minimize the handler codes for finding the port that has generated an interrupt. If this bit
is set to 1, an interrupt has occurred in the port group. Next, check the PPORTPxINTF.PxIFy bit set to 1 in the
port group to determine the port that has generated an interrupt. Clearing the PPORTPxINTF.PxIFy bit also
clears the PPORTINTFGRP.PxINT bit. If the port is set to interrupt disabled status by the PPORTPxINTCTL.
PxIEy bit, the PPORTINTFGRP.PxINT bit will not be set even if the PPORTPxINTF.PxIFy bit is set to 1.
7.6 Control Registers
This section describes the same control registers of all port groups as a single register. For the register and bit con-
figurations in each port group and their initial values, refer to "Control Register and Port Function Configuration of
this IC."
Px Port Data Register
Register name
Bit
PPORTPxDAT
15–8 PxOUT[7:0]
7–0 PxIN[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
*3: The initial value may be changed by the port.
Bits 15–8 PxOUT[7:0]
These bits are used to set data to be output from the GPIO port pins.
1 (R/W): Output high level from the port pin
0 (R/W): Output low level from the port pin
When output is enabled (PPORTPxIOEN.PxOENy bit = 1), the port pin outputs the data set here. Al-
though data can be written when output is disabled (PPORTPxIOEN.PxOENy bit = 0), it does not affect
the pin status. These bits do not affect the outputs when the port is used as a peripheral I/O function.
Bits 7–0
PxIN[7:0]
The GPIO port pin status can be read out from these bits.
1 (R):
Port pin = High level
0 (R):
Port pin = Low level
The port pin status can be read out when input is enabled (PPORTPxIOEN.PxIENy bit = 1). When in-
put is disabled (PPORTPxIOEN.PxIENy bit = 0), these bits are always read as 0.
When the port is used for a peripheral I/O function, the input value cannot be read out from these bits.
Px Port Enable Register
Register name
Bit
PPORTPxIOEN
15–8 PxIEN[7:0]
7–0 PxOEN[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxIEN[7:0]
These bits enable/disable the GPIO port input.
1 (R/W): Enable (The port pin status is input.)
0 (R/W): Disable (Input data is fixed at 0.)
When both data output and data input are enabled, the pin output status controlled by this IC can be
read.
These bits do not affect the input control when the port is used as a peripheral I/O function.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Seiko Epson Corporation
Reset
R/W
H0
R/W
–
H0
R
Reset
R/W
H0
R/W
–
H0
R/W
7 I/O PORTS (PPORT)
Remarks
Remarks
7-7
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