Mx265 - Alinco DJ-G1T Service Manual

7) MX265 (XA0241 )
CTCSS Encoder/Decoder
Xtal/Clock: Input to the on-chip inverter used with a
1 MHz Xtal or external clock source.
Xtal: Output of the on-chip inverter (clock output).
Load/Latch: Controls 8 on-chip latches and is used to
latch RX/TX, PTL, and D0-D5. This pin is internally
pulled to Vdd. A logic "1" applied to this input puts the 8
latches in "transparent" mode. A logic "0" applied to this
input puts the 8 latches in the "latched" mode. Data is
loaded and latched by a 0-1 -0 strobe pulse on this pin.
Serial Enable: A logic "0" applied to this input will
enable serial programming. This pin is internally pulled
to Vdd.
Serial Data Input: This is the serial data input. Data is
loaded in the following order: D5, D4, D3, D2, D1, DO,
RX/TX and PTL. This pin is internally pulled to Vdd.
Serial Clock Input: Data is clocked on the positive
going edge. This pin is internally pulled to Vdd.
Vss: Negative supply.
RX Tone Decode Out: This is the gated output of the
decode comparator. This output is used to gate the RX
Audio path. A logic "0" on this pin indicates a successful
decode and that the Decode Comparator Input pin is
more positive than the Decode Comparator Ref. input.
MX265DW
6Bp
XTAL/CLOCK Vdd
a < 5
'p L i Z l
XTAL TONE IN
LOAD/LATCH BIAS
SERIAL ENABLE R ttTX
SERIAL DATA TONE OUT
SERIAL CLOCK RX DETECT
NC DECODE COMP. IN
VSS RX DECODE
J T
Decode Comparator Input: This is the inverting input
of the decode comparator. This pin is normally
connected to the integrated output of the RX Tone
Detect line.
Rx Tone Detect: In Rx mode this pin will go to logic "1"
during a successful decode. It must be externally
integrated to control response and deresponse times.
Tx Tone Out: The CTCSS sinewave output appears on
this pin under the control of the RX/TX pin. This pin,
when not transmitting a tone, may be biased to Vdd -
0.7V or O /C .
Rx/Tx: This input selects Rx or Tx modes . This
function may be selected by this pin, or It may be serially
loaded. This pin is internally pulled to Vdd via a 1 M C2
resistor.
Bias: This pin is the output of an internally generated
Vdd/2 bias level and would normally be externally
decoupled to Vss via capacitor C6.
Tone Input: This is the input to the CTCSS tone
detector. It is internally biased to Vdd/2.
Vdd: Positive Supply.
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