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BCLK Frequency
The CPU speed is determined by the CPU Ratio multiplied with the BCLK.
Increasing the BCLK will increase the internal CPU clock speed but also affect the
clock speed of other components.
Primary Timing
CAS# Latency (tCL)
The time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
The number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
The number of clock cycles required between the issuing of the precharge command and
opening the next row.
RAS# Active Time (tRAS)
The number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
The delay between when a memory chip is selected and when the first active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
The amount of delay that must elapse after the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time2 (tRFC2)
The number of clocks from a Refresh command until the first Activate command to
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