4.13
TG SCHEMATIC DIAGRAM
0 1 MAIN (TG)
5
TO CCD
CN5201
CN107
[2]
CCD_VL
V1
V1
4
[14, 15]
V2
V2
CCD_VHH
TO TG
V3
V3
V4
V4
TO SYSCON
CCD_CTL
CCD_CTL
TO TG
CCD_15V
CCD_VHH
CCD_15V
GND
GND
CN107
GND
[19]
[17]
[20]
GND
GND
GND
[18]
3
GND
[1]
RG
RG
[5]
[4]
H1
H1
TO TG
[3]
H2
H2
CCD-7V
CCD_VL
SUB
SUB
CN107
TO REG
NQR0129-002X
REG_4.8V
2
C5002
C5001
1
GND
[3.5V_REG]
∗
NOTE : The parts with marked ( ) is not used.
1
A
B
CN107
C5023
VDD3
0.1
SGMOD
VM
V2
V2
V4
V4
CXD3602R
V1
V1
R5001
C5024
VH
0.1
[TG/V_DRIVER]
100k
V3
V3
C5025
SUB
SUB
1
/35
T
RG
VL
C5026
0.1
H1
DSGAT
C5027
H2
VDD4
0.1
C5004
1
L5001
T
T
0.1
C
NOTES :
For the destination of each signal and further line connections that are cut off from
this diagram , refer to "4.1 BOARD INTERCONNECTIONS".
When ordering parts , be sure to order according to the Part Number indicated in the Parts List.
∗
C5014
VDD2
TL5001
0.1
CLM(18M)
TEST2
XPBLK
IC5001
TL5002
XCLPDM
GND(CDS)
R5003
10
XSHD
R5002
10
XSHP
C5013
0.1
AVD(CDS)
XCLPOB
C5012
0.1
AVD(H)
H2
R5020
10
R5010
10
∗
R5006
10
R5009
0Ω
D
E
4-27
4-28
L5004
L5005
10µ
NQR0129-002X
L5006
L5007
10µ
NQR0129-002X
C5018
∗
∗
T
T
∗
∗
∗
T
T
L5002
L5003
10µ
10µ
R5017
220
T
C5009
47
/6.3
T
FBI
OUT2
IN
VDD
∗
GND
OUT1
FS0
FS1
IC5002
W194-70G-X
y30165001a_rev0.1
F
TO SYSCON
TG_RST
CLK_OUT
DATA_OUT
TG_CS
TO CAMERA DSP
HDIN
VDIN
TO REG
REG-CCD
REG_15V
TO CAMERA DSP,
CDS
PBLK
SHD
TO CDS
SHP
TO CAMERA DSP, CDS
CPOB
TO CDS
CCD_3.1V
TO CAMERA DSP
CLK9A
DSP_72M
TG_36M
TO CDS
ADCLK
G
H