Sony CNU-500 Maintenance Manual page 44

IC
TMP82C265BF-2 (5MHz) (TOSHIBA) FLAT PACKAGE
C-MOS PROGRAMMABLE PERIPHERAL INTERFACE
-TOP VIEW-
65
66
67 GND
68
69
70
71
72
73
74
75
76
77
78
79
80
PIN PIN
I/O SIGNAL
I/O SIGNAL
NO. NO.
1 - NC 21 I/O PA12
2 I A1 22 I/O PA11
3 I A0 23 I/O PA10
4 I/O PC07 24 -
5 I/O PC06 25 I
6 - NC 26 I SEL1
7 I/O PC05 27 -
8 I/O PC04 28 I/O PC17
9 I/O PC00 29 I/O PC16
10 I/O PC01 30 I/O PC15
11 I/O PC02 31 I/O PC14
12 - NC 32 I/O PC10
13 I/O PC03 33 I/O PC11
14 - NC 34 I/O PC12
15 I/O PA17 35 I/O PC13
16 I/O PA16 36 I/O PB10
I/O PA15 I/O PB11
17 37
18 - NC 38 I/O PB12
19 I/O PA14 39 I/O PB13
20 I/O PA13 40 I/O PB14
RD WR RESET A0 A1 CS1 SEL1 CS0 SEL0
70 69 68 3 2 25 26 79 80
READ/WRITE
CONTROL LOGIC
BLOCK-1
GROUP B GROUP A
CONTROL CONTROL
GROUP A
GROUP B
PORT C PORT B PORT C PORT A
I/O I/O I/O I/O
PC13-10 PB17-10 PC17-14 PA17-10
35-32 44-42 28-31 15-17
40-36 19-23
4-10
40
39
38
37
36
35
34
33
32
31
30
29
28
GND 27
26
25
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
41 - NC 61 -
42 I/O PB15 62 I/O
43 I/O PB16 63 I/O
NC 44 I/O PB17 64 -
CS1 45 - V 65 I/O
CC
46 - NC 66 I/O
GND 47 I/O PB00 67 - GND
48 I/O PB01 68 I RESET
49 I/O PB02 69 I
50 I/O PB03 70 I
51 - NC 71 I/O
52 I/O PB04 72 I/O
53 I/O PB05 73 I/O
54 - NC 74 I/O
55 I/O PB06 75 I/O
56 I/O PB07 76 I/O
I/O D7 I/O
57 77
58 I/O D6 78 I/O
59 I/O D5 79 I
60 I/O D4 80 I SEL0
D7-D0 GND
27,67
57-60
62,63
65,66
DATA
BUS BUFFER
BLOCK-0
GROUP B GROUP A
CONTROL CONTROL
INTERNAL 8BIT BUS
GROUP B GROUP A
PORT C PORT B PORT C PORT A
I/O I/O I/O
PC03-00 PB07-00 PC07-04
13 56,55 4, 5
11-19 53,52 7, 8
50-47
3 78
A0 PA0
2 77
A1 PA1
76
PA2
25 75
CS1 PA3
79 74
CS0 PA4
73
PA5
26 72
SEL1 PA6
80 71
SEL0 PA7
68 8
RESET PC4
7
PC5
69 5
WR PC6
70 4
RD PC7
66 47
D0 PB0
65 48
D1 PB1
63 49
D2 PB2
62 50
D3 PB3
60 52
D4 PB4
59 53
D5 PB5
58 55
D6 PB6
57 56
D7 PB7
9
PC0
10
PC1
11
PC2
13
NC
PC3
D3
23
D2
PA10
22
NC
PA11
21
D1
PA12
20
D0
PA13
19
PA14
17
PA15
16
WR
PA16
15
RD
PA17
PA7
31
PA6
PC14
30
PA5
PC15
29
PA4
PC16
28
PA3
PC17
PA2
36
PA1
PB10
37
PA0
PB11
38
CS0
PB12
39
PB13
40
PB14
42
PB15
43
PB16
44
PB17
32
PC10
VCC
33
45 PC11
34
PC12
35
PC13
I/O
PA07-00
71-78
INPUT
A0-A1 ; ADDRESS LINE
CS0-CS1 ; CHIP SELECT
RD ; READ CONTROL
R/W ; READ/WRITE CONTROL
RESET ; RESET
SEL ; GENERAL MODE/OUTPUT MODE
SELECT CONTROL
WR ; WRITE CONTROL
INPUT/OUTPUT
D0-D7 ; DATA BUS
PA0-PA17 ; INPUT/OUTPUT PORT A
PB0-PB17 ; INPUT/OUTPUT PORT B
PC0-PC17 ; INPUT/OUTPUT PORT C
TC4W53F (TOSHIBA) CHIP PACKAGE (5.0 × 3.1)
C-MOS 2-CHANNEL MULTIPLEXER / DEMULTIPLEXER
(SCALE 3/1)
6 0
—TOP VIEW—
7 1
1 OPEN
8 V
DD(+3 to +18V)
5 A
7
2
INH
3 6
2
GND 4
5
CONT.INPUT
ON
INH A CHANNEL
0 0 0
0 ; LOW LEVEL
0 1 1
1 ; HIGH LEVEL
1 X OPEN
X ; DON'T CARE
C 1
V
EE
3
CNU-500