Panasonic TH-42PX20U-P Service Manual page 378

D
D-Board(1of2)Block Diagram
LVDS:Low Voltage Differential Signaling
D6
TX0- 2
TX0+ 3
TX1- 5
TX1+ 6
TX2- 8
TX2+
9
TX3- 14
TX3+ 15
TXC- 11
TXC+ 12
TO DG-BOARD
DG3
D3 (1/2)
Y S
40
PB S 38
PR S 36
IC9023
5V->3.3V
HS
HD
34 17 3
VS
VD
32 15 5
CLP
NCLP 31 13 7
IC9711
SWITCHING
SCL1
SDA1 7
SCL1 4 1 2
SDA1 5 6 5
SCL2
6
3 Q9719
SDA2
7
SCL3 8 SCL3
5V->3.3V
SDA3
9 SDA3 Q9704 SCL2(3.3V)
5V->3.3V
SMM
SOUND MAIN MUTE 12 Q9703 SDA2(3.3V)
CABLE DET
CABLE DET 13 SDA2
SCL2
TH-42PX20U-P D-BOARD (1 of 2) BLOCK Diagram
IC9002
IC9005
LVDS/TTL(PARALLEL)
BUS SWITCH
OE
9 1
R/G/B
10 27
11
55
IC9003
12
INVERTER
15
16
2
19
CLK OUT 26
20
HS OUT 3
17
VS OUT
5
18
IC9009
A/D CONVERTER(SUB)
67
PLL
G(8Bit)
G7 2
G
Y/G IN G
48 CLP
G0
9
110M
B(8Bit)
8BIT B7 12
B Pb/B IN
43 CLP B
ADC
B0
19
R Pr/R IN R(8Bit)
R7 70
54 CLP
R
R0
77
VD
VS OUT
SDA2
57 SDA2 64
SYNC/SEPA
HS OUT HD
SCL2
56 SCL2 66
38 30 31
SCL2(IIC 5V)
SDA1(IIC 5V)
IIC_CONT
LSI RESET
IC9709
(1/2)
SUB MPU(CONVERTER)
DATA OUT
MC CLK
D
Q9001
Format Converter
INV.
IC9004
SWITCHING
3
CLKC
4
5 6 DCKC
2 1
8BIT
7
ADC
110M
IC9008
BUS SWITCH
OE
R/G/B
DIGITAL C
27 29
77 DCKC
23 HDS I/O
24 VDS I/O
7 HD
8 VD
3 CLP
206 HS C1
205 VS C1
CLP C1
9
MCDATA
16
147 RESET
MC CLK
20
FPGA-LD
21
SMM
CABLE_DET
IC9706
RESET
RESET
RESET 5V<->3.3V
42
Q9706
SW
DATA IN
11
10
9
IC9702
EEPROM
SDA 5
SCL 6
IC9001
REG 3.3V
(1/2)
P5V 5 4 3.3V
IC9153
REG 5V
IC9151
UNREG 14V 1 3 5V
FORMAT CONVERTER(I/P)
CTI/TINT
B0-B7,G0-G7,R0-R7
RGB COLOR
FORMAT
CONTRAST
CONVERTER
/Y Pb Pr LEFT(MASTER)RGB 8bit
WB-Adj
(I/P
OSD
CONVERTER)
St-r
IC9155
SDRAM I/F
F.CLP 64M SDRAM
IC9154 IC9157
HD
VD OCK PLL
3.3V->5V PLL M
CLK
(100MHz)
IC9014
5V->3.3V
B0-B7,G0-G7,R0-R7
RIGHT(SLAVE)RGB 8bit
SDA2 SDA2
OSD
SCL2
SCL2
185 75 74
SERIAL
OSD
DATA
IC9606
RESET 4
106
RESET
50MHz
CLK
182
IC9605 VD
178
HD 179
SYNC PROCESSOR
OSD (1/2)
SDA I/O 132 SDA2
SCL I/O SCL2
133
IC9703
MCVD 18 15
MCHD 17 17
3.3V->5V
OSD IN0 IC9602
OSD IN7
5V->3.3V
NH IN
61 SOUND MUTE 113
NV IN
111
Q9707 AD1
100
A0
IC9701
A/D SEL.
68
A9
MICRO PROCESSOR
MC CLK
85 D00
FPGA-LD
104
D15
RAS
MCDATA
CAS
MCCLK
86
CE
WE
OE
SCL3
87 SCL3
OSC IN 9
X9701
SDA3 SDA3
88
24.5MHz
SCL2 89 SCL2 OSC OUT 10
SDA2 90 SDA2 OSC IN 38
X9703
SCL1 70 SCL1 20MHz
OSC OUT 39
SDA1 71 SDA1
A01 A19
TH-42PX20U-P D-BOARD (1 of 2) BLOCK Diagram
IC9006 IC9007
REG 3.3V REG 3.3V
P5V 5 4 3.3V P5V 5 4 3.3V
IC9152 IC9302
REG 3.3V REG 3.3V
P5V 5 4 3.3V P5V 5 4 3.3V
CLK
50MHz
IC9303
IC9301
PLL
PLL
50MHz
60MHz
CLK2
6 CLKD 7
65MHz
5 CLK1 XIN 1 6 X OUT CLKE 8
OSC OSC
IN OUT
4 5
X9302
20MHz
IIC_CONT
RESET
SMM
CABLE_DET
HD,VD
3
5
IC9704
VRAM(1Mbit)
IC9705
FLASH MEMORY
(8M ROM)