Mitsubishi MELSEC Q4ARCPU User Manual page 181

Programmable logic controller
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Error
Code
Error Contents and Cause
(SD0)
The contents of the parameter are
3005
broken.
• The high speed interrupt is set in a
Q02CPU.
• The high speed interrupt is set in a
multiple CPU system.
3006
• The high speed interrupt is set when
aQA1S6 B or QA6 B is used.
• No module is installed at the I/O
address designated by the high
speed interrupt.
The parameter file in the drive specified
as valid parameter drive by the DIP
3007
switches is inapplicable for the CPU
module.
In a multiple CPU system, the modules
3009
for AnS, A, Q2AS and QnA have been
set to multiple control CPUs.
*3
The module whose first 5 digits of serial No. is 04012 or later.
*4
The module whose first 5 digits of serial No. is 07032 or later.
*5
The MELSECNET/H module whose first 5 digits of serial No. is 08102 or later.
*6
The module whose first 5 digits of serial No. is 09012 or later.
*7
The Universal model QCPU except the Q02UCPU.
Corrective Action
• Read the individual information of the
error using the peripheral device,
check the parameter item
corresponding to the numerical value
(parameter No.), and correct it.
• Write the modified parameter items to
the CPU module again, and power-on
the PLC or reset the CPU module.
• When the same error occurs again,
the hardware is faulty. Contact your
local Mitsubishi representative,
explaining a detailed description of
the problem.
• Delete the setting of the Q02CPU' s
high speed interrupt. To use high
speed interrupts, change the CPU
module to one of the Q02H/Q06H/
Q12H/Q25HCPU.
• To use a multiple CPU system, delete
the setting of the high-speed
interrupt. To use high speed
interrupts, change the system to a
single CPU system.
• To use either the QA1S6 B or
QA6 B, delete the setting of the high
speed interrupt. To use high speed
interrupts, do not use the QA1S6 B/
QA6 B.
• Re-examine the I/O address
designated by the high speed
interrupt setting.
Create parameters using GX
Developer, and write them to the drive
specified as valid parameter drive by
the DIP switches.
Re-set the parameter I/O assignment to
control them under one CPU module.
(Change the parameters of all CPUs in
the multiple CPU system.)
168
Corresponding
CPU
*6
Qn(H)
*3
Qn(H)
QnPRH
*1
Qn(H)

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