Table of Contents
Advertisement
QK01 : AK4528
AINL+
AINL-
ADC
AINR+
AINR-
VCOM
AOUTL+
AOUTL-
DAC
AOUTR+
AOUTR-
VREF
Control Register I/F
VA
AGND
P/S
CSN
CCLK
CDTI
(DIF)
(CKS1)
(CKS0)
No.
Pin Nam e
I/O
Common Vo ltage Output Pin, VA /2
1
V COM
O
Bias voltage of A DC inputs and DA C outputs.
2
A INR+
I
Rch Positive Inp ut Pin
3
A INR-
I
Rch Negative Inp ut Pin
4
A INL +
I
L ch Positive Inp ut Pin
5
A INL -
I
L ch Negative Inp ut Pin
Vo ltage Reference Input Pin, VA
6
V REF
I
Used as a voltage reference by A DC & DA C. VR EF is connected externally to
filtered VA .
7
A GND
-
A nalog Ground Pin
8
V A
-
A nalog Power Supply Pin, 4.75 ~ 5.25V
Parallel/Serial Mode Select P in
9
P /S
I
ì L î: Serial Mode, ì Hî: P arallel Mode
10
MC L K
I
Master Clock Input Pin
11
LRCK
I
Input/Outp ut Channel Clo ck Pin
12
BICK
I
A udio Serial Data Clo ck Pin
13
SDT O
O
A udio Serial Data Output Pin
14
SDT I
I
A udio Serial Data Inp ut Pin
CDTI
I
Control Data Input Pin in Seri al Mode
15
CKS0
I
Master Clock Select Pin
CCLK
I
Control Data Clock Pin in Serial Mo de
16
CKS1
I
Master Clock Select Pin
CSN
I
Chip Select Pin in Serial Mode
17
Dig ital A udio In terface Select P in
DIF
I
ì L î: 24bit MSB justif ied, ì Hî: I
18
DFS
I
Double Speed Sampling Mo de Pin
Power-Down M ode Pin
19
PD N
I
ì Hî: P ower up, ì L î: P ower down reset and initialize the co ntrol register.
20
DEM0
I
De-emphasis Control Pin
21
DEM1
I
De-emphasis Control Pin
22
VT
-
Output Buffer Power Supply Pin, 2.7 ~ 5.25V
23
VD
-
Digital Power Supply Pin, 4.75 ~ 5.25V
24
DGND
-
Digital Grou nd Pin
25
A OUT L -
O
L ch Negative Analog Output Pin
26
A OUT L +
O
L ch Positive A nalog Output Pin
27
A OUT R-
O
Rch Negative Analog Output Pin
28
A OUT R+
O
Rch Positive A nalog Output Pin
Note: A ll input pins should not be left f loating.
VCOM
1
VD
AINR+
2
VT
3
AINR-
DGND
PDN
AINL+
4
HPF
AINL-
5
LRCK
Audio I/F
BICK
6
VREF
Controller
SDTO
AGND
7
SDTI
DATT
VA
8
SMUTE
P/S
9
DEM0
MCLK
10
Clock Divider
DEM1
LRCK
11
BICK
12
SDTO
13
MCLK
DFS
SDTI
14
Function
Pin 1 index mark,
notched corner, or both
D14/RDY
D13/ C/D
MUTE/GPIO5
D12/ERR
GPIO4
D11/PP7
GPIO3
D10/PP6
2
S compatible
51
28
AOUTR+
27
AOUTR-
26
AOUTL+
25
AOUTL-
24
DGND
AK4528
VD
23
Top
22
VT
View
21
DEM1
20
DEM0
19
PDN
18
DFS
17
CSN(DIF)
16
CCLK(CKS1)
15
CDTI(CKS0)
100
81
1
80
A0
SDB
GND
SDC
SS
GND
TMS
A19
INT
A18
VDD
A17
D18
GND
D19
A1
CLKOUT
A2
GND
A3
VDDA
VDD
FLTCAP
GNDA
VDD
SCKIN
A4
GND
VDD
XTI
ZR38601
XTO
GND
P/M
(TOP VIEW)
A5
SPFRX
A6
BYPASS
VDD
DREQ/GPIO0
A7
ERROR/GPIO1
A8
GPIO2
VDD
A9
SDD
A10
GND
GND
CS
VDD
WR
30
51
31
50
Q651:ZR38601
Host
4
A
Serial Host
Internal
Internal Program/
Serial Audio
E
SPI or Z2C
Data RAM
Data RAM
Inputs
Serial
Interface
10k x 20
2k x 32
F
Input
f
AUDIO
Ports
S/PDIF
S/PDIF
Input
Receiver
ZR38001
4
Control
DSP Core
Parallel Host
Interface
Input Data
Data/
16
Parallel
FIFO
Control
Port
8 x 9
f
DSP
System
ICE
GPIO
Oscillator &
Memory
20
Interface
DSP PLL
Address
Interface
4
6
Test
General Purpose
Xtal
I/O Ports
Figure 5. ZR38601 Simplified Block Diagram
ZR38601 Signal Description Summary
[1]
Name
Number
Type
Parallel Port (40)
A[19:0]
20
O
Address bus of parallel port
D[19:15]
5
I/O
Data bus of parallel port when selected for external memory (P/M = 0)
D14/RDY
1
I/O or O
Data bus (P/M = 0) or Ready output signal of parallel port when selected for parallel I/O (P/M = 1)
D13/ C/D
1
I/O or I
Data bus (P/M = 0) or Command/Data select input of parallel port when selected for parallel I/O (P/M = 1)
D12/ERR
1
I/O or I
Data bus (P/M = 0) or Error input signal of parallel port when selected for parallel I/O (P/M = 1)
D[11:4]/PP[7:0]
8
I/O
Data bus of parallel port when selected for external memory (P/M = 0) or Parallel Port I/O (P/M = 1)
CS
1
I/O
Chip Select output for external memory or Chip Select input for parallel I/O
RD
1
I/O
Read enable output for external memory or Read enable input for parallel I/O
WR
1
I/O
Write enable output for external memory or Write enable input for parallel I/O
P/M
1
I
Parallel I/O or Memory select for parallel port. Determined at time of RESET.
Serial Ports (13)
SPFRX
1
I
S/PDIF Receiver input port
SDA, SDE, SDF
3
I
Serial Data inputs. Ports A, E and F.
WSA/FSA
1
I/O
Word Select or Frame Synchronization for input ports. An output when a master, an input when a slave.
SCKA
1
I/O
Serial Clock for input ports. An output when a master, an input when a slave.
SDB
1
O
Serial left and right Data output. Port B. Also, at RESET defines SPI/Z2C for host serial interface.
SDC
1
O
Serial left and right surround Data output. Port C. Also, at RESET defines Z2CADR[0] of Z2C address.
SDD
1
O
Serial center and sub-woofer Data output. Port D. Also, at RESET defines Z2CADR[1] of Z2C address.
SDG/SPFTX
1
O
Serial Data output. Port G or S/PDIF Transmitter port. Also, at RESET defines the SCKP value.
WSB/FSB
1
I/O
Word Select or Frame Synchronization for output ports. An output when a master, an input when a slave.
SCKB
1
I/O
Serial Clock for output ports. An output when a master, an input when a slave.
SCKIN
1
I/O
Serial master Clock output or master clock Input for output ports
General Purpose Ports (6)
MUTE/GPIO5
1
I or I/O
Mute input signal or can be programmed as General Purpose Input/Output 5
GPIO[4:2]
3
I/O
Can be programmed as General Purpose Input/Output 4, 3 and 2
ERROR/GPIO1
1
O or I/O
Error output signal or can be programmed as General Purpose Input/Output 1
DREQ/GPIO0
1
O or I/O
Data Request output signal or can be programmed as General Purpose Input/Output 0
Serial Host Interface (4)
SI
1
I
Host Serial interface data Input. Also, at RESET defines Z2CADR[5] of Z2C address.
SO/SDA
1
I/O/T
SPI host Serial interface data Output or Serial Data for Z2C
SCK/SCL
1
I
SPI host Serial interface Clock input or Slave Clock input for Z2C
SS
1
I
SPI host serial interface Slave Select input. Also, at RESET defines Z2CADR[4] of Z2C address.
ICE Interface (4)
TDI
1
I
ICE Test interface Data Input
TDO
1
O/T
ICE Test interface Data Output
TCK
1
I
ICE Test interface Clock input
TMS
1
I
ICE Test interface Mode Select
System Interface (7)
INT
1
I
External Interrupt request input
RESET
1
I
Reset input to start operation in known state
XTI
1
I
External system clock Input or connection to external crystal, at frequency f
XTO
1
O
Output connection to external crystal
CLKOUT
1
O
Clock Output from the ZR38601 at frequency f
BYPASS
1
I
Bypass internal DSP core PLL to use external system clock input on XTI
FLTCAP
1
I
External Filter Capacitor connection for PLL. A value of 47nF is recommended.
Power (26)
VDD
12
Power
+3.3 volt power supply
VDDA
1
Power
+3.3 volt power supply, Analog for PLL
GND
12
Power
Power supply Ground
GNDA
1
Power
Power supply Ground, Analog for PLL
Total (100)
1. O = Output, I = Input, T = Tri-state in normal use. May be different at Reset time as shown in Table 23 on page 42.
52
Internal Program/
Data ROM
20k x 32
S/PDIF
S/PDIF or
G
Transmitter
Left/Right Center
Serial
Output
B
Left/Right
Ports
Serial Audio
Outputs
C
Left/Right Surround
D
Center/Subwoofer
f
AUDIO
Audio PLL
Timer
Description
XTI
/2
DSP
Advertisement
Table of Contents
