Circuit Descriptions - Philips TPS2.1E LA Service Manual

7. Circuit Descriptions

Index of this chapter:
7.1 Introduction
7.2 Main Supply
7.3 On-Board Platform Supply
7.4 On-board DC/DC Converters
7.5 MST9A885GL
Notes:
• Only new circuits (circuits that are not published recently)
are described.
• Figures can deviate slightly from the actual situation, due
to different set executions.
• For a good understanding of the following circuit
descriptions, please use the wiring, block (chapter 6) and
circuit diagrams (chapter 7). Where necessary, you will find
a separate drawing for clarification.
7.1 Introduction
This chassis is a derivative from theTPS1.2E LA chassis .It
comes with styling called "TPS2.1E LA" for sets from the
XXPFL3404 series.
It's built around the MST9A885GL-LF "System on Chip" (SoC).
Tuner
PC
HDMI
SCART
YPbPr
USB2.0
Circuit Descriptions
7.1.1 Features
The main features for this chassis are:
•
7.1.2 Click Architecture Overview
For details about the chassis block diagrams refer to chapter
"Block diagrams, Test Point Overview, and Waveforms". An
overview of the xxPFL3404 architecture can be found in next
figure "Architecture of xxPFL3404 platform". Sets with all
resolutions @ 60 Hz use the MST9A885GL SoC. With the
same configuration, a resolution of 1360x768p @ 59.79 Hz, or
even 1920 × 1080p@60 Hz can be achieved.
PANEL
LVDS
MST9A885GL
Figure 7-1 System architecture.
TPS2.1E LA
High performance back-end processing Perfect Pixel HD
engine capable of 300 Mpixels/sec. With this technology,
each pixel of the incoming picture is enhanced to better
match the surrounding pixels, resulting in a more natural
picture. Artifacts and noise in all sources from multimedia
to standard TV to highly-compressed high-definition (HD)
are detected and reduced. This results in a clean and razor
sharp image.
WT6703F
DDR or SD-RAM
NVRAM
Audio AMP
Pre- AMP
18250_202_090210.eps
7. EN 19
090318
2009-Apr-10