Ic Pin Function Description - Sony ICF-CD543RM Service Manual

ICF-CD543RM

5-12. IC PIN FUNCTION DESCRIPTION

• LCD BOARD IC401 µPD789477GC-A16-8BT (SYSTEM CONTROLLER)
Pin No. Pin Name
1, 2 NC
3 to 5 VLC0 to VLC2
6 to 9 COM0 to COM3
10 to 25 SEG0 to SEG15
NC
26 to 32
33 OPEN S/W
34 CLOSE S/W
35
TRAY OPEN
36
TRAY CLOSE
37 NC
38 AVDD
39
ENCODE +
40
ENCODE –
41 OPTION
42 to 44 KEY0 to KEY2
RST
45
46 DRF
47 AVSS
48 RC
49 AC IN
50 WRQ
51 FSEQ
52 BUZZER
53 C LAT
54 C DATA
55 C CLK
56 C DATA IN
57 XRST
58 VR DATA
59 VR CLOCK
60 POWER ON
61 R DATA
62 R CLK
63 R DATA IN
64 R CE
TRAY MUTE
65
NC
66
SHIFT 0
67
68 SHIFT 1
69 IC
70 TX1
71 TX2
32
I/O
— Not used
—
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
O Common drive signal output to the liquid crystal display
O Segment drive signal output to the liquid crystal display
— Not used
Detection input from the tray open/close detect switch
I
"L": when tray is open, "H": when tray is close
Detection input from the tray open/close detect switch
I
"L": when tray is close, "H": when tray is open
O Motor drive signal output to the disc tray open/close motor driver "H" table out
O Motor drive signal output to the disc tray open/close motor driver "H" table in
— Not used
— Power supply terminal (+3.3V) (analog system)
I Jog dial pulse input terminal
I Jog dial pulse input terminal
I Destination setting terminal Not used
I Key input terminal (A/D input)
— Not used
I Focus on/off detection signal input from the digital signal processor
— Ground terminal (analog system)
I Remote control signal input from the remote control receiver
I Power failure detection signal input terminal "L": power failure, "H": power on
I Interruption detection signal input from the digital signal processor
I Synchronizing signal detection signal input from the digital signal processor
O Buzzer sound drive signal output
O Chip enable signal output to the digital signal processor
O Serial data output to the digital signal processor
O Serial data transfer clock signal output to the digital signal processor
I Serial data input from the digital signal processor
O Reset signal output to the digital signal processor "L": reset
O Volume data output
O Volume clock signal output
O Power amplifier on/off control signal output "L": standby mode, "H": power amplifier on
O Serial data output terminal Not used
O Serial data transfer clock signal output to the FM/AM PLL
I Serial data input from the FM/AM PLL
O Chip enable signal output to the FM/AM PLL
O Not used
— Not used
— Not used
— Not used
— Internal connection terminal
I Sub system clock input terminal (32.768 kHz)
O Sub system clock output terminal (32.768 kHz)
Description