Denon AVR-X3500H Service Manual page 56

Pin Pin Name Symbol I/O Pu/Pd
142 VCC VCC -
143 PD7/IRQ7/AN107 DIR_CE O
144 PG1 DIR_DOUT I DA3.3Pu
145 PD6/IRQ6/AN106 DIR_CLK O
146 PG0 DIR_RST O
147 PD5/IRQ5/AN113 787_HAINT
I -
148 PD4/IRQ4/AN112 ZVOL_STB
O
149 P97 DE_RST
O Pd
150 PD3/IRQ3/AN111 787_HINT
I -
151 VSS VSS
-
152 P96 787_RST
O Pd
153 VCC VCC
-
154 PD2/IRQ2/AN110 788_2_HINT
I -
155 P95 788_2_RST
O Pd
156 PD1/IRQ1/AN109 788_1_HINT
I -
157 P94 788_1_RST
O Pd
158 PD0/IRQ0/AN108 TTL_SEL_B
O
159 P93/AN117 THERMAL_A I SW3VPu
160 P92/RXD7/AN116 THERMAL_F I SW3VPu
161 P91/AN115 TTL_SEL_A O -
162 VSS VSS -
TEMP_SEN-
163 P90/TXD7/AN114 I
SOR
164 VCC VCC -
P47/IRQ15-DS/
165 ARC_INT
I
AN007
P46/IRQ14-DS/
166 CURRENT_DET
I/O
AN006
P45/IRQ13-DS/
167 AMPSIGDET
I
AN005
P44/IRQ12-DS/
168 MODE
I
AN004
P43/IRQ11-DS/
169 KEY3
I M3VPu
AN003
P42/IRQ10-DS/
170 KEY2 I M3VPu
AN002
P41/IRQ9-DS/
171 KEY1 I M3VPu
AN001
172 VREFL0 VREFL0 -
173 P40 ADC_RST O
174 VREFH0 VREFH0 -
175 AVCC0 AVCC0
-
176 P07/IRQ15 Z2PLD_ERR
I -
CEC
STBY STOP Function
STBY
- - - Power supply pin
L L L DIR (PCM9211) control pin
I I I DIR (PCM9211) control pin
L L L DIR (PCM9211) control pin
L L L DIR (PCM9211) control pin
HDMI Rx (MN864787) audio interrupt signal det
Z -
ZONE2 volume control pin (NJW1194)
L L L
Video decoder (ADV7180) reset control pin
Z L
HDMI Tx (MN864787) interrupt signal input pin
Z -
Ground pin
- - -
HDMI Tx (MN864787) reset control pin (When CEC
Z H
standby mode3,set to reset)
Power supply pin
- - -
HDMI Rx (MN864788) interrupt signal input pin
Z - -
HDMI Rx (MN864788) reset control pin (When CEC
Z - H
standby mode3,set to reset)
HDMI Rx (MN864788) interrupt signal input pin
Z - -
HDMI Rx (MN864788) reset control pin (When CEC
Z - H
standby mode3,set to reset)
Video PLD control pin(select for A to H/NET/HDMI)
L L L
I L I Protection detect signal input pin (for power TR)
I L I Protection detect signal input pin (for power TR)
L L L Video PLD control pin(select for A to H/NET/HDMI)
- - - Ground pin
I L I Temperature sensor input pin (for SRM)
- - - Power supply pin
ARC IC interrupt signal input pin
L L L
Current level monitor pin (A/D converter)
I/L L/L I/L
Signal level monitor pin (AD converter)
I L I
Region setting pin
I I I
Key control signalinput pin (When standby mode,set to
I I I
inturrupt)
Key control signalinput pin (When standby mode,set to
I I I
inturrupt)
Key control signalinput pin (When standby mode,set to
I I I
inturrupt)
- - - Ground pin
I L I A/D convertor(AK5358) reset control pin
- - - Power supply pin
Power supply pin
- - -
Detect ZONE2 DIR error (from Audio PLD)
L L L
AD8195
AD8195ACPZ (INPUT : U1022)
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN0 1
IN0 1
IP0 2
IP0 2
IN1 3
IN1 3
IP1 4
IP1 4
VTTI 5
VTTI 5
IN2 6
IN2 6
IP2 7
IP2 7
IN3 IN3 8 8
IP3 9
IP3 9
AVCC 10
AVCC 10
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
NOTES
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
Terminl Function
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type 1
1 IN0 HS I
2 IP0 HS I
3 IN1 HS I
4 IP1 HS I
5 VTTI Power
6 IN2 HS I
7 IP2 HS I
8 IN3 HS I
9 IP3 HS I
10, 16, 22, 23, 25, 26, 30 AVCC Power
11 ON0 HS O
12 OP0 HS O
13 VTTO Power
14 ON1 HS O
15 OP1 HS O
17 ON2 HS O
18 OP2 HS O
19 ON3 HS O
20 OP3 HS O
21 COMP Control
24, 27, 37, Exposed Pad AVEE Power
28 TX_EN Control
29 PE_EN Control
31 CEC_OUT LS I/O
32 AMUXVCC Power
Block diagram
PARALLEL
VTTI
+
IP[3:0]
–
IN[3:0]
VREF_IN
SCL_IN
SDA_IN
CEC_IN
56
30 AVCC
PIN 1
30 AVCC
29 PE_EN
INDICATOR
PIN 1
29 PE_EN
INDICATOR
28 TX_EN
28 TX_EN
27 AVEE
27 AVEE
26 AVCC
AD8195
26 AVCC
AD8195
TOP VIEW 25 AVCC
TOP VIEW 25 AVCC
(Not to Scale) (Not to Scale)
24 AVEE
24 AVEE
23 AVCC 23 AVCC
22 AVCC
22 AVCC
21 COMP
21 COMP
Figure 3. Pin Configuration
Description
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Positive Analog Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
Output Termination Supply. Nominally connected to AVCC.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Power-On Compensation Pin. Bypass to ground through a 10 μF capacitor.
Negative Analog Supply. 0 V nominal.
High Speed Output Enable Parallel Interface.
High Speed Preemphasis Enable Parallel Interface.
CEC Output Side.
Positive Auxiliary Buffer Supply. 5 V nominal.
Rev. 0 | Page 6 of 20
AVCC
AD8195
AMUXVCC
AVEE
CONTROL
LOGIC
VTTO
4 4 +
OP[3:0]
BUFFER
4 4 –
EQ PE
ON[3:0]
HIGH SPEED BUFFERED
VREF_OUT
2 2 SCL_OUT
SDA_OUT
CEC_OUT
LOW SPEED BUFFERED
BIDIRECTIONAL