Denon AVR-X4500H Service Manual page 190

fig.V03
AVRX4500H/SR7013/AV7705/SR6013 HDMI BLOCK
HDMI SW2(MN864788)
P3 RX
H D MI IN1
(CBL/SAT)
MAIN
P2 RX
H D MI IN2
(DVD)
SUB
P1 RX
H D MI IN3
(BLU-RAY)
P0 RX
H D MI IN4
(GAME)
VDD33, VDD33IO, AVDD33TX, AVDD33RX, PVDD33 : 3.3V
VDD11, AVDD11RX, AVDD11TX : 1.1V
H D MI IN5
(MED IA Player)
H D MI IN6
(AUX2)
H D MI IN7
(CD)
H D MI IN8
(AUX1)
DEC_PB_IN
DEC_PR_IN
DEC_CVBS_IN
Z2_HAINT
Z2H DMISPDIF
EHARC_SD0~3
EHARC_MCK, EHARC_BCK, EHARC_LRCK
EHARC_SPDIF
EHARC_MUTE
RXI2S0~3, RXSPDIF
RXMCK, RXBCK, RXLRCK, RXINT0
TXDATA0
TXBCK, TXLRCK
LEGO_RGB Date(24bit)
LEGO_Date Enable
LEGO_Vsync
LEGO_H sync
LEGO_PCK
P0 TX
P1 TX
VDD33, VDD33IO, AVDD33TX, AVDD33RX, PVDD33 : 3.3V
VDD11, AVDD11RX, AVDD11TX : 1.1V
HDMI SW1(MN864788)
P3 RX
MAIN
P0 TX
P2 RX
SUB
P1 RX
P1 TX
P0 RX
ADV7180
DVDD, PVDD, AVDD : 1.8V
DVDDIO : 3.3V
DEC_Y_IN
EARC_P, EARC_N
EHARC
EHARC_RST #158
EHARC_INT #165
SiI9437
AVSCL #78
AVSDA #77
IOVCC33, AVCC33 : 3.3V
AVCC12, CVCC12, PVCC12 : 1.2V
HDMI TX(MN864787)
P1 RX
P0 RX
H D MI Rx 600MHz
4K/2K
Rxlink0
P3 RX
Up Scaler
Matrix SW
VDD33, VDD33IO, AVDD33TX, AVDD33RX, PVDD33 : 3.3V
VDD11, AVDD11RX, AVDD11TX : 1.1V
EARC_P, EARC_N
RXI2S0~3, RXSPDIF
RXMCK, RXBCK, RXLRCK, RXINT0
TXDATA0
TXBCK, TXLRCK
VIDEO PLD
DO8~15, LLC
LEGO_RGB Date(24bit)
LEGO_Date Enable EPM570F256C4N
LEGO_Vsync
LEGO_H sync
LEGO_PCK VCCINT, VCCIO : 3.3V
AD55/058Z-0(ADV8003-8B)
Video Processor(1080P, OSD, IP Conv,)
DVDD_IO, AVDD1, AVDD2 : 3.3V
AVDD3, DVDD, CVDD1, PVDD1-3,PVDD5-6 : 1.8V
CONTROL
VDD, VDDQ, VDDL : 1.8V
VREF : 0.50xVDDQ
S. FLASH
D D R2 SD RAM
MX25L12835FMI-10G
A3R12E40DBF-8E
VCC : 3.3V
128M 512M
190
H D MI ZONE2
600MHz
P1 TX
Txlink0 H D MI Tx
H D MI OUT1
4K/2K
PTX1_HPD
Matrix SW
600MHz
P0 TX
H D MI OUT2
Txlink1
4K/2K
ARC
D D R2 INTERFACE
VDD, VDDQ, VDDL : 1.8V
VREF : 0.50xVDDQ
D D R2 SD RAM
A3R12E40DBF-8E
512M