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2.9 Service processor
The service processor is an embedded controller based on a PowerPC 405GP processor
(PPC405) implementation running the service processor internal operating system. The
service processor operating system contains specific programs and device drivers for the
service processor hardware.
The key components include a flexible service processor-base (FSP-B) and an extender
chipset (FSP-E). Figure 2-10 illustrates the service processor.
HMC
Ports
R ack Ind C onn
Figure 2-10 Service processor block diagram
The flexible service processor core is a five-stage pipeline instruction processor and contains
32-bit general purpose registers. The flash ROM contains a compressed image of a software
load.
Service processor
block diagram
RISC Watch
Conn
32.768 KHz
R TC
OSC
R J-45
E net #1
Broadcom
P H Y
R J-45
E net # 2
4 M Hz
TO D /SIT
OSC
D S
U AR T
1-wire
#3
U AR T
U AR T
#1
#2
S1-rear
XCVR
DB9
S2-rear
XCVR
DB9
PCI-X at 100 MHz
Flash ROM
40 MB or48 MB
Flash
N VR AM
ALE
Interface
Base
D D R Interface
DDR
(FSP-B)
64 M B
I2C
E ngines
JTAG
E ngines
U AR T
IN TR
#4
Secondary
Secondary
PCI
PCI
PCI Bus
U AR T #5, P ort0
Extender
(FSP-E)
U AR T #1-2,
7-9
Chapter 2. Architecture and technical overview
NVRAM
Controller
SRAM
1 M B
4 I2C
Engines
2 JTAG
E ngines
8
Interrupts
U AR T #3
U AR T #3
U AR T #4
X /R
X /R
PS1
M U X
T o Sm artchip VP D Serial
U AR T #6
M U X
GP IO
GP IO
I2C
6 I2C Engines
E ngines
JTAG
8 JTAG E ngines
E ngines
5 Interrupts
IN TR
25
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