JVC GZ-MG21AC Service Manual page 43

MAIN(V I/O) SCHEMATIC DIAGRAM
DV2OUT0
DV2OUT1
DV2OUT2
DV2OUT3
TO DSP
DV2OUT4
DV2OUT5
DV2OUT6
DV2OUT7
TO MPEG2,DSP
DV2CKOUT
VI0
VI1
VI2
VI3
VI4
TO MPEG2
VI5
VI6
VI7
MPGFLD
MPGVSYNC
MPGHSYNC
IC3202
MB90099PFV139EX
1 SCLK HD 20
2 CS VD 19
3 SIN VC0 18
4 RST VC1 17
5 VDD VC2 16
6 SDR BLKA 15
C3219 7 NC VC3 14
0.1
8 EXD BLKB 13
9 TEST TSTO 12
ANA_RST 10 GND BLKC 11
TO SUB CPU
ANA_IN
TO MAIN IF(CN101), ANA_OUT
SUB CPU,AUDIO
ANA_CLK
ANA_CS
TO SUB CPU OSD_CS
OSD_VD
TO SUB CPU,DSP
DSP_RST
TO SUB CPU PSCTL
L3201
NQR0129-002X
TO OP DRV
ASPECT
TO MAIN IF,
REG+CCD
C3220
CDS/TG
4.7
REG_4.9V
REG_3.1V
TO MPEG2,
SREG2.5V
DSP MEM
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
180 179 178 177 176 160 96 51 132 159 95 50 131 94 49 130 93 48 92
1 NC1
2 NC1
13 NC1
14 NC1
R3201
54 VSS
0Ω
3 RST
3 6
97 CSO0
4 5
55 CSO1
RA3201
1 8
133 CSO2
10
2 7
99 CSO3
3 6
4 YSO0
4 5
98 YSO1
RA3202
1 8
134 YSO2
10
2 7
56 YSO3
C3201 0.01
5 VDD(I/O)
TL3201 100 OUTH
R3202 0Ω
135 OUTV
TL3202
6 OUTH2
R3203 0Ω
57 OUTV2
TL3204
101 ZCNT (L:OUTV,OUTH=HiZ)
R3204 0Ω
7 SDOUT
58 VDD(CORE)
C3202 0.01
102 VSS
136 CLK
R3205 0Ω
8 SDIN
R3206 0Ω
59 SCLK
R3207 0Ω
103 CS
9 VC0
60 VC1
137 VC2
104 VC3
10 BLK1
61 BLK2
138 BLK3
11 HDOUT
62 VDOUT
R3208 100
105 CLKOSD
139 HDCVF
12 VDCVF
63 VSS
161 NC2
162 NC2
163 NC2
164 NC2
165 NC2
15 26 27 28 106107140 65 16 141 66 17 108 67 18 142109 19 68 143110 20 69 144 21 70 111 71 22 112145 23 146 72 25 24 73 113114 74 166167168169170
R3209 0Ω
R3224
33
(1608)
R3223
100 Q3202
2SC4617/QR/-X
L3203
NQR0129-002X
C3224
1
47 158 129 157 46 91 128 45 90 156 127 44 89 126 43 155 88 125 124 42 87 154 86 75 64 53
NC2 175
NC2 174
NC2 173
NC2 172
NC2 171
VSS 85
VSS(8AD) 38
C3215 OPEN
VDD(8AD) 123
CIN 84
VRH 37
C3214 OPEN
VRL 153
VRM 122
C3213 OPEN
VDD(8AD) 36
VSS(8AD) 83
C3212 SHORT
VYIN 121
CLPY 82
R3215 2.7k
IREF1 35
_0.5%
YCOUT 152
ABAR1 120
C3211 1
COMP1 34
IC3201 YSOUT 81
C3210 0.1
VREF1 151
VSS(10DA) 80
JCP8075
C3209 0.1
VDD(10DA) 33
NC 119
NC 150
NC 32
NC 79
VSS(8DA) 118
VDD(8DA) 149
R3214 2.7k
IREF2 31
_0.5%
CROUT 78
ABAR2 117
C3208 1
COMP2 148
CBOUT 77
VREF2 116
COUT 147
C3207
VDD(8DA) 115
0.01
VSS(8DA) 30
SCANI3 29
C3206
VDD(CORE) 76
0.1
NC1 52
NC1 41
NC1 40
NC2 39
R3212 R3213
18k 12k
_0.5% _0.5%
IC3204
R1100D251C-X
1 2 3
L3206
SHORT
(2125)
C3230
OPEN
(2125)
C3227 C3225
OPEN OPEN
(No.YF137)2-13 2-14(No.YF137)
0
R3218 R3219
OPEN OPEN
R3222
C3703
Short
1
Q3201
OPEN IC3701
L3701
BH7612FV-X
1 4 R3221
Short 10µ
2 5
C3701 C3702
6 3 10/6.3 T 0.1
R3216 R3217
820 820
_0.5% _0.5%
16 15 14 13 12 11 10 9
GND VCC PSCTRL GND PVCC
LPF
5
7dB
200k
BPF 1.8k
1
20k
GND PGND
1 2 3 4 5 6 7 8
C3704
0.01
6 4
2 5
Q3701
BC847PN-X
1 3
R3709
1.2k
R3710
2.2k
L7851
SHORT
L7801
22µ
C7852
OPEN
R7805 R7810 R7815
R7801 12k 12k 12k
33k _0.5% _0.5% _0.5%
6 3 6 3 6 3
2 5 2 5 2 5
1 4 Q7801 1 4 Q7802 1 4 Q7803
C7801 C7802 UMX1N-W UMX1N-W UMX1N-W
4.7/16 1/16
C7804
1/16
C7805
1/16
R7804 R7809 R7814
C7806
2.2k 2.2k 2.2k
1/16
_0.5% _0.5% _0.5%
R7802 R7803 R7807 R7808 R7812 C7803 R7813 R7817
8.2k 620 8.2k 620 6.8k 1 620 6.8k
_0.5% _0.5% _0.5%
1 MAIN(V I/O)
4
R3701
0Ω
Y_OUT
D3701
TO MAIN IF
UMZ6.8EN-W
V_OUT
(CN101)
R3702 C_OUT
0Ω
2 3
C3705 R3703
0.01 68 _0.5%
R3708
10k
R7851 R7854 R7857
33k 33k 33k
_0.5% _0.5% _0.5%
MON_G
MON_R
TO MAIN IF
MON_B
(CN101,110)
HRP
VDCVF
TO MAIN IF
HDCVF
(CN101)
R7853 R7856 R7859
36k 36k 36k
_0.5% _0.5% _0.5%
yf137_y10618001a_rev0.1