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Chapter 5 Input/Output Interfaces
Main Status Register, I/O Port 3F4h/374h (Read Only)
Bit
Function
7
Request for Master. When set, indicates the controller is ready
to send or receive data from the CPU. Cleared immediately
after a byte transfer. Indicates interrupt pin status during non-
DMA phase.
6
Data I/O Direction.
0 = Expecting a write
1 = Expecting a read
5
Non-DMA Execution. When set, indicates controller is in the
execution phase of a byte transfer in non-DMA mode.
4
Command In Progress. When set, indicates that first byte of
command phase has been received. Cleared when last byte in
result phase is read.
3..0
Drive Busy Indicators. Bit is set after the last byte of the
command phase of a seek or recalibrate command is given by
the corresponding drive:
<3>, Drive 3
<2>, Drive 2
<1>, Drive 1
<0>, Drive 0
Data Register, I/O Port 3F5h/375h
Data commands are written to, and data and status bytes are read from this register.
Data Transfer Rate Register, I/O Port 3F7h/377h (Write Only)
Bit
Function
7
Software Reset
6
Low Power Mode (if set)
5
Reserved
4..2
Write Precompensation Delay
000 = Default values for selected data rate (default)
1,0
Data Rate Select:
00 = 500 Kb/s
01 = 300 Kb/s
10 = 250 Kb/s
11 = 1 or 2 Mb/s (depending on TUP reg. Bit <1>)
5-12
Compaq Deskpro 4000 and 6000 Personal Computers
featuring the Pentium II Processor
First Edition – October 1997
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