Philips P&S 22HFL4372D/10 Service Manual page 50

EN 50 8. Q552.1HE LA
8.8 Diagram Ethernet + Service
Block diagram
MODE0
MODE1
MODE Control
MODE2
nRST
RMIISEL
TXD[0:3]
TXEN
TXER
TXCLK
RXD[0:3]
RXDV
RXER
RXCLK
CRS
COL/CRS_DV
MDC
MDIO
Pinning information
2010-Nov-19
IC Data Sheets
B04C, LAN8710A-EZKH (IC 7E10)
Auto-
Negotiation
Reset
Control
Management
SMI
Control
100M Rx DSP System:
Logic
Data Recovery
Receive Section
10M Rx
Logic
VDD2A 1
LED2/nINTSEL 2
LED1/REGOFF 3
XTAL2 4
XTAL1/CLKIN 5
VDDCR 6
RXCLK/PHYAD1 7
RXD3/PHYAD2 8
Figure 8-8 Internal block diagram and pin configuration
10M Tx 10M
Logic Transmitter
Transmit Section
100M Tx 100M
Logic Transmitter
Analog-to-
Clock
Digital
Equalizer
100M PLL
Squelch &
Filters
10M PLL
SMSC
LAN8710/LAN8710i
32 PIN QFN
(Top View)
VSS
back to
div. table
HP Auto-MDIX
MDIX
Control
PLL
Interrupt
Generator
LED Circuitry
Central
Bias
PHY
Address
Latches
24 TXD2
23 TXD1
22 TXD0
21 TXEN
20 TXCLK
19 nRST
18 nINT/TXER/TXD4
17 MDC
TXP / TXN
RXP / RXN
XTAL1/CLKIN
XTAL2
nINT
LED1
LED2
RBIAS
PHYAD[0:2]
18770_302_100217.eps
100217