Power Supply Voltage Sequence - NEC NL204153BM21-01 Datasheet

4.4 POWER SUPPLY VOLTAGE SEQUENCE

VDD
Note1
LVDS Signals *1,*2
Note2
CS, SCLK, SDAT
Note2
*1: DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/-, CKB+/-,
DC0+/-, DC1+/-, DC2+/-, DC3+/-, CKC+/-, DD0+/-, DD1+/-, DD2+/-, DD3+/-, CKD+/-
*2: LVDS signals should be measured at the terminal of 100 resistance.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 10.8V, a protection
circuit may work, and then this product may not work.
Note2: LVDS signals and CS, SCLK, SDAT must be Low or High-impedance, exclude the VALID
period (See above sequence diagram), in order to avoid that internal circuits is damaged.
If some of signals are cut while this product is working, even if the signal input to it once again,
it might not work normally. VDD should be cut when the display and function signals are
stopped.
Note3: At the beginning of the serial communication mode, take 20ms or more after the LVDS signal
input. When writing the LUT data, see "4.12 TEN-bit LOOK UP TABLE FOR GAMMA
ADJUSTMENT".
Note4: The backlight should be turned on within the valid period of display and function signals, in
order to avoid unstable data display.
VDD ON
10.8V
0V
5ms < Tr < 80ms
0V
0V
10ms < t < 35ms
10ms < t < 35ms
DATA SHEET DOD-PD-1318 (4th edition)
NL204153BM21-01/01A
10.8V
9.6V
VDD dip < 20ms
VALID period
Note3
t 20ms
VALID period
VDD OFF
VDD ON
Toff > 50ms
0ms < t < 35ms
10.8V
11