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4.2
Driver Circuit Description
The supply voltage and input signals for driver U1 and bias supply U2 are applied through header J1.
Capacitors C3, C7, and C8 are located as close as possible to the VCC1 and GND1 terminals of U1 and
U2, to minimize EMI while operating as part of high dv/dt and di/dt power system. Resistors R2 and R3
and capacitors C1 and C2 provide additional filtering to protect input signals. These filters are optional and
may not be used in the systems where noise is limited. The secondary side noise decoupling is provided
by capacitors C2, C6, C9, C10, and C11. Split outputs of the driver U1 through gate resistors R1 and R4
are connected to FETs Q1 and Q2. These FETs are not populated on the board and their through hole
footprints are used to solder the board for evaluation on a system level, as it is shown in
board, the gate resistors have been selected at 1 Ω. However, as was described in
resistor values determine switching rise and fall time with the power losses inside the driver IC, therefore
their values can be changed for specific requirements. Capacitor C5 can be used to estimate drive current
capability by measuring rise and fall time using the board separately. It is not populated on boards
intended to be used in a power system.
4.3
FET Recommendation
This board can be used with both IGBT and MOSFET-based power systems. FET selection does not
impact the board maximum power. The UCC5390S device limits the power dissipated by the board.
4.4
Bias Supply Circuit and Setting Description
By default, the bias supply outputs are set for 18 V turn ON voltage and –4V turn OFF voltage. The output
split rail is provided by Zener diode D5, resistor R5, and capacitors C6 and C11, with jumpers R7 and R6
removed. If a different turn OFF voltage is needed, a proper voltage-rated Zener diode and resistor can be
selected. If a split rail is not needed, then jumper R7 must be placed on the board and resistor R5 can be
removed. This will reduce overall power consumption initially dissipated inside resistor R5 and Zener
diode D5. Another bias supply option is possible by configuring the rectifier circuit as center-tapped or
bridge. Bridge configuration is provided by removing jumper R6. In this case, for the same input voltage
VCC, the output bias voltage is doubled versus the center-tapped rectifier. For the center-tapped rectifier,
the diodes D1 and D3 must be removed, and jumper R6 placed onboard.
combinations of bias voltages, depending on nominal input voltage and rectifier configurations. These
voltages obviously depend on the transformer turn ratio. For this board, a transformer, 750342879, from
Würth-Midcom with a turn ratio 1:3.5 has been selected.
Configuration
Center-tapped, single
output
Bridge, single output
Center-tapped, split output
Bridge, split output
SLLU282A – December 2017 – Revised February 2018
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Table 3. Bias Voltage Configurations
Modification
Remove D1, D3, R5; place R7 and
R6
Remove R5 and R6; place D1, D3,
R7
Remove D1, D3, R7; place R5 and
R6
Remove R7 and R6; place D1, D3,
R5
Copyright © 2017–2018, Texas Instruments Incorporated
Section
Table 3
lists possible
Input (V)
3.6
5
3.3
5
3.6
5
3.3
5
UCC5390SCD With Isolated Bias Supply
Detailed Description
Figure
5. On this
4.1, gate
Output (V)
11
17
22
34
+7/–4
+13/-4
+18/-4
+30/–4
7
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