Figure 4–7. External Reference – Input Span and Bias Set by on Board Reference Circuit
(potentiometer P2 sets EXT_T, potentiometer P3 sets EXT_B)
AIN
2 V
PP
MODE
VREF
REFSENSE
AVDD
THS1030/31
SHA
PGA
A/D
ADC
REF
–
+
+
_
1 V
REFBF
REFTF
REFTF
EXT_T
0.1 µF
10 µF
0.1 µF
EXT_B
REFBF
0.1 µF
Modes of Operation
4-5