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Chapter 4 Award BIOS Setup
5. DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing.
6. Bank Interleave
7. Precharge to Active (Trp)
8. Active to Precharge (Tras)
This item controls the number of DRAM clocks for TRAS.
9. Active to CMD (Trcd)
10. DRAM Command Rate
This item set the DRAM command rate.
AGP & P2P BRIDGE CONTROL:
The options for these items are found in its sub menu. By pressing the
<ENTER> key, you are prompt to enter the sub menu of the detailed options
as shown below:
AGP Aperture Size
AGP Driving Control
X AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
↑↓→←:Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
Descriptions on each item above are as follows:
1. AGP Aperture Size
This field determines the effective size of the Graphic Aperture used
for a particular GMCH configuration. It can be updated by the
GMCH-specific BIOS configuration sequence before the PCI standard
bus enumeration sequence takes place. If it is not updated then a
default value will select an aperture of maximum size.
Page: 4-14
Phoenix – Award CMOS Setup Utility
AGP & P2P Bridge Control
[64M]
[Audo]
DA
[Disabled]
[Disabled]
[Disabled]
F6:Fail-Safe Defaults
Item Help
Menu Level ►
F7:Optimized Defaults
PSB-1688LF USER
'
S MANUAL
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