Ic Pin Function Description - Sony SMP-N100 Service Manual
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Also See for SMP-N100:
- Operating instructions manual (63 pages) ,
- Specifications (1 page) ,
- Instruction & operation manual (14 pages)
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MAIN SYSTEM CONTROL PIN FUNCTION (MB-136 BOARD IC101: CXD9983GG/CXD9984GG)
Pin
Symbol
A1
FESFDO
A3
VOUTD1
A5
VOUTD5
A7
VOUTD9
A9
VOUTD12
A11
VIND0
A13
VIND12
A15
VIND16
A17
GPIO1
A19
SPDIF
A21
SPBCK
A23
AVDD12_27 MPLL
A25
NS_XTALI
A27
CH1_M
A29
CLK_M
A31
DACOUT4
A33
DACOUT1
A35
VCLK
A37
UARXD
A39
ETRXD3
A41
ETRXD0
A43
ETRXCLK
B2
FESFCS
B4
VOUTD3
B6
VOUTD7
B8
VOUTD10
B10
VOUTD14
B12
VIND4
B14
VIND14
B16
VINHSYNC
B18
GPIO3
B20
SPLRCK
B22
AOBCK
B24
AVDD12_DMPLL
B26
CH2_M
B28
CH0_M
B30
EXT_CAP
B32
DACOUT3
B34
VDATA
B
3
6
R I
B38
ETMDIO
B40
ETRXD1
B42
ETRXER
C1
FE_SFCLK
C3
FESFDI
C5
VOUTD4
C7
VOUTD8
C9
VOUTD11
C11
VOUTD15
C13
VIND11
C15
VIND15
C17
GPIO0
C19
GPIO2
C21
SPMCLK
C23
AOSDATA0
C
2
5
N
S
_
X
T
A
L
O
C27
CH1_P
C29
CLK_P
C31
DACOUT5
C33
DACOUT2
C35
MRESET_
C37
ETCOL
C39
ETRXD2
C41
ETTXCLK
C43
ETTXD0
D2
FE_GIO11
D4
FESFCK
D6
VOUTD6
D8
VOUTD0
D10
VOUTD13
D12
VIND1
D14
VIND13
D16
VINCLK
D18
VIND17
D20
AOSDATA5
SECTION 6
IC PIN FUNCTION DESCRIPTION
Type
Description
I/O
Serial Data Input to Front_End Serial Flash
I/O
NC
I/O
NC
I/O
NC
I/O
NC
NC
I/O
I/O
NC
NC
I/O
GPIO
I/O
START-BIT
I/O
SPDIF Digital Audio Out
I/O
SPDIF in Bit Clock
Power
1.2V Analog Power for PLL
O
27MHz Crystal Out
Analog
HDMI TX data 1 differential pair (M)
Analog
HDMI TX clock differential pair (M)
Analog
DAC Output
Analog
DAC Output
I/O
VFD Clock (IF_SCK)
RS232 RX
I/O
CPU_UARXD
I/O
Receive Data from the PHY
I/O
Receive Data from the PHY
I/O
Receive Clock from the PHY
I/O
Front-END Serial Flash Chip Select
I/O
NC
I/O
NC
I/O
NC
I/O
NC
GPIO
I/O
DAC_XRST
I/O
NC
I/O
NC
GPIO
I/O
USB_VBUS_PCONT2
I/O
SPDIF in Left-Right Clock
I/O
Audio Out Bit Clock
Power
1.2V Analog Power for DMPLL
Analog
HDMI TX data 2 differential pair (M)
Analog
HDMI TX data 0 differential pair (M)
Analog
NC
Analog
DAC Output
I/O
VFD Data (IF_SDO)
/ I
O
Infrared Input
Management Data INPUT/OUTPUT from/to the MDIO pin
I/O
I/O
Receive Data from the PHY
Receive Error Signal from the PHY
I/O
Serial Flash's Clock OUTPUT
I/O
NC
I
Serial Data Output to Front-END Serial Flash
NC
I/O
I/O
NC
NC
I/O
I/O
NC
I/O
NC
I/O
NC
GPIO
I/O
SYSCON_REQ
GPIO
I/O
XIF_CS
I/O
SPDIF in Master Clock
I/O
Audio Out Serial Data 0
I
2
7
M
H
z
C
y r
t s
l a
n I
Analog
HDMI TX data 1 differential pair (P)
Analog
HDMI TX clock differential pair (P)
Analog
DAC Output
Analog
DAC Output
O
Front-End Power ON Reset
Collision Detect From the PHY
I/O
I/O
Receive Data from the PHY
Transmit Clock from the PHY
I/O
I/O
Transmit Data from the PHY
UTXD.
3.3V LVTTL I/O,
FE RS232 Serial Transmit data.
NC
Front-END Serial Flash Clock
I/O
I/O
NC
I/O
NC
I/O
NC
NC
I/O
I/O
NC
NC
I/O
I/O
NC
I/O
Audio Out Serial Data 5
6-1
SMP-N100
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