Samsung DVD-A500 Service Manual page 62

6-6-2 NTSC/PAL Digital Encoder (TIC50 : SAA7128)
TIC1 inputted from pin4 with 27MHz generates HSYNC and VSYNC which are based on video signal. Each HSYNC
and VSYNC outputted from Pin8 and Pin7 are inputted to Pin157 and Pin158 of A/V decoder VIC1(ZIVA-3). VIC1
is the synchronous signals with the video signal and control the output timing of 8bit video signal of ITU-R601 for-
mat. (Pin180, 182, 184 ~ 189 (MSP))
8bit data is inputted to Pin9(MSB) and Pin16 of TIC1 and the inputted data is demuxed with each 8bit of Y/R-Y/B-
Y. The separate signal is encoded to NTSC or PAL by control of MIC1. The above signals, that is CVBS
(Composite Video Burst Synchronized)(Pin30), S-Video (Y:Pin27, C:Pin24), Y/Pb/Pr(Pin27/Pin29/Pin23) and
GB(Pin26/Pin29/Pin23). In course of encoding, 8bit data can extend to 10bit or more. To convert the extended data
to quantization noise as possible, TIC1 adopts 10bit D/A converter. TIC1 perform video en-coding as well as copy
protection.
CR-CB
VDATA
[7:0]
Y
9~16
VSYNC
7
HSYNC
8
27M
4
MRST 40
SDA 42
SCL
41
6-6-3 Amplifier (TIC2, TIC3 : BA7660)
TIC2 and TIC3 are 6dB amplifier. Based on CVBS signal, the final output level must be 2Vpp without 75ohm ter-
minal resistance. Because the level of video encoder output is only 1.1Vpp, the level is adjusted with the special
amplifier. When mute of pin1 is high active, if the pin is floating and connected to power, the output signal is never
outputted. CVBS, Y, C, Pr and Pb outputted from video encoder are inputted to TIC2 (Pin7, Pin2 and Pin4) and TIC3
(Pin7, Pin2 and Pin4) respectively and outputted from TIC2 (Pin10, Pin15 and Pin13) and TIC3 (Pin10, Pin15 and
Pin 13). Pin9, Pin12 and Pin14 of TIC3 and TIC2 are feedback pin to SAG compensation(DC characteristic compen-
sation of signal). Resistance (TR201 ~ TR206, TR303 ~ TR308) which is inserted to input terminal is bias resistance
for input offset.
The signal to which gain is adjusted by amplifier is outputted from jack via 75ohm.
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TIC1 (SSA7128)
RGB encoding
Luminace
processing
MACROVISION Cloed captions
7.0.1/6.1 CGMS
Chrominance
processor
CTRL+CFG
register
Fig. 6-22
30
27
24
Trap
23
26
29
Circuit Descriptions
CVBS
Y
C
Pr/R
G
Pb/B
6-17