1. Manuals
  2. Brands
  3. Emerson Manuals
  4. Control Unit
  5. COM Express Carrier
  6. Design manual

Emerson COM Express Carrier Design Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
COM Express Carrier Type 2
Design Guide
October 2009
Confidential and Proprietary

Advertisement

Table of Contents
loading

Related Manuals for Emerson COM Express Carrier

Summary of Contents for Emerson COM Express Carrier

  • Page 1 COM Express Carrier Type 2 Design Guide October 2009 Confidential and Proprietary...
  • Page 2 All the material herein is Emerson Confidential Proprietary and is subject to Emerson standards for controlling proprietary material. Use of this material is restricted to Emerson employees with a need to know, and others with a need to know that are subject to a confidentiality agreement.

  • Page 3: Table Of Contents

    3.4.3 X1 Slot Example ......................23 3.4.4 x4 Slot.........................24 3.4.5 Express Card Example....................24 3.4.6 PCI Express Mini Card ....................26 PCI Express Signals—Routing Consideration........27 PCIe Graphics (PCIe 16—31) and SDVO ....29 COM Express Carrier Type 2 Page 3 of 103 Design Guide...
  • Page 4 Example Schematic ...............38 Layout Consideration..............38 USB Ports.............39 USB Carrier Signals Definition ............39 Reference Schematic ..............40 Layout Consideration..............40 SATA..............41 SATA Signals Definition..............42 Reference Schematic ..............43 Layout Consideration..............44 LVDS..............45 LVDS Signals Description ...............45 Page 4 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 5 5-pin Compact Flash Header...................56 10.3 Layout Consideration..............57 PCI...............58 11.1 PCI Signals Definition..............58 11.2 PCI Resource Assignment...............62 11.3 Reference Schematic ..............62 11.3.1 Device-Down example....................62 11.3.2 PCI Bus Slot Example....................64 11.4 Layout Consideration..............64 COM Express Carrier Type 2 Page 5 of 103 Design Guide...
  • Page 6 14.3 Layout Consideration..............75 SM bus and I C .............76 15.1 Signals Definition ................76 15.2 I C Address Allocation Consideration..........76 15.3 Layout Consideration..............77 Miscellaneous Signals ..........78 16.1 Module Type Detection..............78 Page 6 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 7 BIOS Consideration..........88 19.1 Legacy versus Legacy Free .............88 19.2 Carrier Super I/O Support...............88 Mechanical Consideration ........89 20.1 Form Factor...................89 20.2 Heat Spreader ................90 Layout Guidelines ..........91 21.1 PCB Stack-ups................91 COM Express Carrier Type 2 Page 7 of 103 Design Guide...
  • Page 8 LVDS Trace Routing Guidelines ................101 21.4 Routing Rules for Single-Ended Interfaces ........101 21.4.1 PCI Trace Routing Guidelines................102 21.4.2 IDE Trace Routing Guidelines ................103 21.4.3 LPC Trace Routing Guidelines................103 Page 8 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 9 Thermal Management Signal Description ..............85 Table 26 Approximate Copper Trace Current Capability Per IPC-2221 Charts ......87 Table 27 Trace Parameters ......................94 Table 28 PCI Express 1.1 Trace Routing Guidelines..............96 COM Express Carrier Type 2 Page 9 of 103 Design Guide...
  • Page 10 LVDS Trace Routing Guidelines ................. 101 Table 34 PCI Trace Routing Guidelines ..................102 Table 35 IDE Trace Routing Guidelines ..................103 Table 36 LPC Trace Routing Guidelines..................103 Page 10 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 11 LPC Firmware Hub—Carrier Board BIOS Schematic ............67 Figure 25 LPC Super I/O Example ....................68 Figure 26 AC’97 Schematic Example...................71 Figure 27 Audio Amplifier ......................71 Figure 28 HDA Example Schematic .....................72 Figure 29 TV-Out Reference Schematic..................75 COM Express Carrier Type 2 Page 11 of 103 Design Guide...
  • Page 12 Six Layer Stack-Up....................... 91 Figure 39 Eight Layer Stack-Up ....................92 Figure 40 Microstrip Cross Section ..................... 93 Figure 41 Stripline Cross Section ....................93 Figure 42 Layout Considerations ....................95 Page 12 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 13: About This Document

    COM Express- based system. 1.2 Intended Audience The intended audience of this document are COM Express carrier board designers. It is strongly recommended to use the latest COM Express Specification and the module vendor’s product manuals with this document.
  • Page 14 A non-profit industry trade group that issues and maintains technical standards to manufacturers of embedded and industrial computer boards and systems. SATA Serial AT Attachment A high-speed serial-interconnect standard for hard disks. SATA is electrically quite Page 14 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 15 LVDS. TMDS uses 8b/10b encoding to achieve DC balance and is used for DVD-D displays Universal Serial Bus A hot-pluggable serial I/O interconnect standard. VESA Video Electronics Standards Association An industry trade group that issues standards for CRT and flat-panel displays. COM Express Carrier Type 2 Page 15 of 103 Design Guide...

  • Page 16: Carrier Board Connector

    PCB connector pattern are in the correct positions (as shown in the land pattern of the COM Express specification) and if the holes are drilled to the proper size and tolerance by the PCB fabricator. Page 16 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 17: Figure 1 Com Express Type 2 Connector

    Figure 1 COM Express Type 2 Connector COM Express Carrier Type 2 Page 17 of 103 Design Guide...

  • Page 18: Pci Express Lanes 0-5

    The COM Express Specification does not allocate any module pins for strapping PCIe lane width options. Table 2 PCIe Signal Definition Signal Description Comment PCIE_RX0+ PCIe channel 0. Receive Input I PCIE PCIE_RX0- differential pair. Page 18 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 19 Reset output from module to O CMOS carrier board. Active low. Issued Suspend by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a COM Express Carrier Type 2 Page 19 of 103 Design Guide...

  • Page 20: Pcie Feature Support

    For information on the supported number and configuration of PCI Express lanes of a specific COM Express module, see the corresponding user’s manual or contact an Emerson Application Engineer. The PCI_RESET# or CB_RESET# either can be used as PCI Express device reset input.

  • Page 21: Figure 2 Pci Express Clock Reference Schematic

     The CLKREQ0# and CLKREQ1# should be pulled low to enable the corresponding clock buffer outputs. For applications in which power management is not a concern, these inputs may be tied low to permanently enable the outputs. COM Express Carrier Type 2 Page 21 of 103 Design Guide...

  • Page 22: Pcie Signals Ac Couple

    The coupling caps for the COM Express module PCIe TX lines are defined by the COM Express Specification to be on the module. Page 22 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 23: X1 Slot Example

    Suspend event, report errors, accept control parameters, return status information and card information such as a serial number. Support for the SMBus is optional on the slot card. COM Express Carrier Type 2 Page 23 of 103 Design Guide...

  • Page 24: X4 Slot

    ExpressCards are the successor to Card Bus cards (which are PCI-based). Card Bus cards, in turn, are the successors to PCMCIA cards. All three formats are defined by the PCMCIA Consortium. The source specification document for ExpressCards is the ExpressCard Standard. Page 24 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 25: Table 3 Support Signals For Expresscard

    Nets PCIE_TX2+ and PCIE_TX2- are sourced from the COM Express module. These lines drive the PCIe receivers on the ExpressCard. No coupling capacitors are required on the carrier board. These lines are capacitively coupled on the COM Express module. COM Express Carrier Type 2 Page 25 of 103 Design Guide...

  • Page 26: Pci Express Mini Card

    PCI Express Card host should offer both interfaces. The PCI Express Mini Card installed into the socket may use either interface. The source specification for PCI Express Mini Cards is the PCI Express Mini Card Electromechanical Specification. Page 26 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 27: Pci Express Signals-Routing Consideration

     Control trace length according to “PCI Express insert loss budget” in the COM Express Specification.  Differential Impedance: 100 ohm ± 15%  Differential pair-to-pair spacing: minimum 20mils COM Express Carrier Type 2 Page 27 of 103 Design Guide...
  • Page 28  TX+ and TX- signals should maintain symmetry when changing layers.  No tight bend, use two 45° bends instead of 90° routing.  Trace length compensation should be added to the short side after each bend. Page 28 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 29: Pcie Graphics (Pcie 16-31) And Sdvo

    Output Differential Pair SDVOB_GRN+ SDVOB_GRN- PEG_RX2+ PEG Channel 2, Receive I PCIE Shared with: PEG_RX2- Input Differential Pair SDVOB_FLDSTALL+ SDVOB_ FLDSTALL- PEG_TX2+ PEG Channel 2, Transmit O PCIE Shared with: COM Express Carrier Type 2 Page 29 of 103 Design Guide...
  • Page 30 PEG Channel 8, Transmit O PCIE PEG_TX8- Output Differential Pair PEG_RX9+ PEG Channel 9, Receive I PCIE PEG_RX9- Input Differential Pair PEG_TX9+ PEG Channel 9, Transmit O PCIE PEG_TX9- Output Differential Pair Page 30 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 31 PEG_ENABLE# PEG enable function. strap I 3.3V to enable PCI Express x16 CMOS external graphics interface. Pull low to disable internal graphics and enable the x16 interface. COM Express Carrier Type 2 Page 31 of 103 Design Guide...

  • Page 32: Pcie Graphics (Peg) Configuration

    23 and an x4 link over lanes 24 through 27. This is module and chipset dependent. PEG_ENABLE# should be left open when the PEG lanes are to be used for general purpose PCIe links. Page 32 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 33: Schematic Examples

    4.2 Schematic Examples 4.2.1 x16 PCIE Graphic Card Figure 8 x1, x4, x8, x16 Slot COM Express Carrier Type 2 Page 33 of 103 Design Guide...

  • Page 34: Sdvo To Dvi Inverter

    4.2.2 SDVO to DVI Inverter Figure 9 SDVO to DVI Transmitter Example (Part 1) Page 34 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 35: Routing Consideration

    There should be a minimum distance of 30 mils between the DVI trace and any ground on the same layer. For more information, refer to the layout and routing considerations as specified by the manufacturer of the SDVO-to-DVI transmitter. COM Express Carrier Type 2 Page 35 of 103 Design Guide...

  • Page 36: Table 5 Sdvo Layout Requirement

    Table 5 SDVO Layout Requirement Page 36 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 37: Lan

    The corresponding LAN differential pair and control signals can be found on rows A and B of the module's connector. See Table Table 6 LAN Interface Signal Description COM Express Carrier Type 2 Page 37 of 103 Design Guide...

  • Page 38: Emerson Lan Led Definition

    The four status signals driven by the COM Express module to the carrier board are low frequency signals that do not have any signal integrity or trace routing requirements beyond generally accepted design practices for such signals. Page 38 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 39: Usb Ports

    Wake-on-USB. The amount of current available on VCC_5V_SBY is limited so it should be used sparingly. 6.1 USB Carrier Signals Definition All eight USB carriers appear on the COM Express A-B connector as shown in Table 7. Table 7 USB Signals Definition COM Express Carrier Type 2 Page 39 of 103 Design Guide...

  • Page 40: Reference Schematic

    Keep layer transitions to a minimum. Reference USB pairs to a power plane if necessary. The power plane should be well-bypassed. Section 21.3.2 USB Trace Routing Guidelines summarizes the USB routing rules. Page 40 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 41: Sata

    SATA. A specific eSATA connector was designed to meet these needs. The eSATA connector does not have the L-shaped key, and because of this, SATA and eSATA cables cannot be interchanged. Figure 13 SATA Connector COM Express Carrier Type 2 Page 41 of 103 Design Guide...

  • Page 42: Sata Signals Definition

    7.1 SATA Signals Definition Table 8 SATA Signal Definition Table 9 SATA Connector Pinout Table 10 SATA Power Connector Pinout Page 42 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 43: Reference Schematic

    The second connection is actually a no-connect on the package and allows for straight-through routing for the SATA differential pairs.  Nets SATA0_TX+/- through SATA1_TX +/- are sourced from the COM Express module SATA TX pins. COM Express Carrier Type 2 Page 43 of 103 Design Guide...

  • Page 44: Layout Consideration

    Keep layer transitions to a minimum. Reference SATA pairs to a power plane if necessary. The power plane should be quiet and well bypassed. SATA-150 routing rules are also summarized in Section 21.3.6 Serial ATA Trace Routing Guidelines. Page 44 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 45: Lvds

    C interface that may be used to support EDID or other panel information and identification schemes. Additionally, there are LVDS power enable (LVDS_VDD_EN) and backlight control and enable lines (LVDS_BKLT_CTRL and LVDS_BKLT_EN). COM Express Carrier Type 2 Page 45 of 103 Design Guide...

  • Page 46: Connector And Cable Considerations

    The cables and connectors that are to be utilized should have a differential impedance of 100 ohms, ±15%. They should not introduce major impedance discontinuities that cause signal reflections. For Page 46 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 47: Display Timing Configuration

    Figure 15 supports this. A header is used to allow the user to configure the type of backlight inverter signal used. In the example, a DAC from Maxim is used (MAX5362 http://www.maxim.com). COM Express Carrier Type 2 Page 47 of 103...

  • Page 48: Color Mapping And Terms

    If you use a flat panel with an integrated LVDS receiver, it is important that the display’s color-mapping matches the module’s color mapping. Page 48 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 49: Table 12 Lvds Display Terms And Definitions

    Terms Definition Table 12 LVDS Display Terms and Definitions COM Express Carrier Type 2 Page 49 of 103 Design Guide...

  • Page 50: Reference Schematic

    All LVDS pairs should have the same environment, including the same reference plane and the same number of vias. LVDS routing rules are summarized in Section 21.3.7 LVDS Trace Routing Guidelines. Page 50 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 51: Vga

    The three analog VGA signals (VGA_RED, VGA_GRN, VGA_BLU) and the two sync signals (VGA_HSYNC and VGA_VSYNC) should be routed as single-ended signals with a trace impedance of 75 ohms. The COM Express Carrier Type 2 Page 51 of 103 Design Guide...
  • Page 52 Level shifters for the DDC interface signals are required between the COM Express module signal side and the signals on the standard VGA connector on the carrier board. Page 52 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 53: Ide And Compact Flash

    For module Types 2 and 4, IDE support is required; LAN 1 and 2 are not available. The IDE (PATA) signals support up to two devices in a master/slave configuration. Table 13 IDE Signals Description COM Express Carrier Type 2 Page 53 of 103 Design Guide...

  • Page 54: Reference Schematic

    Jumper settings on the IDE devices determine master/slave configuration. The drive activity LED is driven by the module's pin A28 (COM Express pin ATA_ACT#). Page 54 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 55: 44-Pin Ide Header

    Because 44-conductor cables have no method of indicating their transfer rate capability, IDE_CBLID# must be controlled on the carrier board or by using BIOS setup. For 44-pin ATA devices, the drive activity LED is driven by pin 39 of the header. COM Express Carrier Type 2 Page 55 of 103 Design Guide...

  • Page 56: 5-Pin Compact Flash Header

    CompactFlash (CF) cards with DMA capability require that the two signals IDE_REQ and IDE_ACK# are routed to the CF card socket on the COM Express carrier board. If this is not done then some DMA capable CF cards may not work because they are not designed for non-DMA mode. For more information about this subject, refer to the data sheet of the CF card or contact your CF card manufacturer.

  • Page 57: Layout Consideration

    The IDE signals are single-ended signals with a nominal impedance of 55 ohms. See Section 20.4.2 'IDE Trace Routing Guidelines' on page xxx for more information about routing considerations. COM Express Carrier Type 2 Page 57 of 103 Design Guide...

  • Page 58: Pci

    PCI_AD10 PCI bus multiplexed I/O 3.3V address and data lines PCI_AD11 PCI bus multiplexed I/O 3.3V address and data lines PCI_AD12 PCI bus multiplexed I/O 3.3V Page 58 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 59 PCI bus multiplexed I/O 3.3V address and data lines PCI_AD29 PCI bus multiplexed I/O 3.3V address and data lines PCI_AD30 PCI bus multiplexed I/O 3.3V address and data lines COM Express Carrier Type 2 Page 59 of 103 Design Guide...
  • Page 60 PCI bus master request I 3.3V input line, active low PCI_GNT0# PCI bus master grant O 3.3V output line, active low PCI_GNT1# PCI bus master grant O 3.3V output line, active low Page 60 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 61 66 MHz operation. It is pulled to ground by the carrier board device or by slot card, if one of the devices is NOT capable of 66 MHz operation. COM Express Carrier Type 2 Page 61 of 103 Design Guide...

  • Page 62: Pci Resource Assignment

    The COM Express PCI interface supports up to four bus master capable PCI bus slots or external PCI devices designed on the COM Express carrier board. The PCI interface is specified to be +5 V tolerant, with +3.3 V signaling. All necessary PCI bus pull-up resistors must be included on the COM Express module.

  • Page 63: Figure 21 Pci Clock Buffer Circuitry

    These parameters are very critical for EMI and must be observed during carrier board layout when implementing the PCI Bus. Figure 21 PCI Device Down Example (Dual UART) COM Express Carrier Type 2 Page 63 of 103 Design Guide...

  • Page 64: Pci Bus Slot Example

    PCI clock signals should be routed as a single ended trace with a trace impedance of 55 ohms. To reduce EMI, a single ground referenced internal layer is recommended. The clock traces should be Page 64 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 65 COM Express Carrier Type 2 Page 65 of 103 Design Guide...

  • Page 66: Lpc

    12.1 LPC Signals Definition Table 16 LPC Interface Signal Implementing external LPC devices on the COM Express carrier board always requires customization of the COM Express module's BIOS in order to support basic initialization for those LPC devices. Otherwise the functionality of the LPC devices will not be supported by a plug and play or ACPI-capable system.

  • Page 67: Figure 24 Lpc Firmware Hub-Carrier Board Bios Schematic

    If low, it is in the firmware hub configuration. For normal operation on a carrier board, this pin should be tied low.  FWH pin 31 is the clock input. The clock source is the LPC_CLK signal from the COM Express module. COM Express Carrier Type 2 Page 67 of 103 Design Guide...

  • Page 68: Super Io Schematic

    - SIO signals may be up to 5 V; COM Express levels must be 3.3 V maximum. Gates may be left off for completely legacy free system. Page 68 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 69: Layout Consideration

    PCI clock above. This provides a separate copy of the LPC clock to each target. The overall delay from the module LPC clock pin to the target LPC device clock pin should be 1.6 ns. COM Express Carrier Type 2 Page 69 of 103 Design Guide...

  • Page 70: Ac'97 And Hd Audio

    HD interfaces to audio codecs on the carrier board. The pins are available on all module types. High- definition (HD) audio uses the same digital-signal interface as AC ’97 audio. Codecs for AC ’97 and HD audio are different. Table 17 Audio Codec Description of Signals Page 70 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 71: Reference Schematic

    13.2 Reference Schematic Figure 25 AC’97 Schematic Example Figure 26 Audio Amplifier COM Express Carrier Type 2 Page 71 of 103 Design Guide...

  • Page 72: Layout Consideration

     Place the crystal or oscillator (depending on the codec used) as close as possible to the codec.(HDA implementations generally do not require a crystal at the codec) Page 72 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 73 EMI emissions and degrade the analog and digital signal quality. COM Express Carrier Type 2 Page 73 of 103 Design Guide...

  • Page 74: Tv Out

    Only one output mode can be used at any given time. 14.1 TV-Out Signals Definition Table 18 TV-Out Definition of Signals Page 74 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 75: Reference Schematic

    Out connector on the carrier board. The PI-filters should be separated from each other by at least 50 mils or more in order to minimize crosstalk between the TV-DAC channels. COM Express Carrier Type 2 Page 75 of 103 Design Guide...

  • Page 76: Sm Bus And I C

    SPD (serial presence detect 1010 000x, 1010 001x), programmable clock synthesizers (1101 001x), clock buffers (1101 110x), thermal sensors (1001 000x), and management controllers (vendor-defined address). Page 76 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 77: Layout Consideration

    Suspend rail to other supplies. Do not use the same address that the module has already used for carrier located devices. COM Express Carrier Type 2 Page 77 of 103...

  • Page 78: Miscellaneous Signals

    Table 21. Module Type 1 has no encoding. For more information about this subject, refer to the COM Express specification. Page 78 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 79: Power Management Signals

    ACPI-defined system states S0 to S5, including the corresponding power rail state. For more information about ACPI and the system power states, refer to the Advanced Configuration and Power Interface Specification, Revision 3.0. COM Express Carrier Type 2 Page 79 of 103 Design Guide...

  • Page 80: Table 22 System States S0-S5 Definitions

    Table 22 System States S0—S5 Definitions Table 23 Power Management Signal Description Page 80 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 81: Watch Dog

    The SPKR signal is often used as a configuration strap for the module’s chipset. It should not be connected to a pull-up or pull-down resistor, which could overwrite the internal chipset configuration and result in a malfunction of the module. COM Express Carrier Type 2 Page 81 of 103 Design Guide...

  • Page 82: Rtc Battery

    Express module will be inaccurate due to current leakage on the module side. When the system is running, this current leakage loads the capacitor of the battery circuitry. This leads to a higher voltage on the signal pin VCC_RTC and therefore produces inaccurate monitoring results. Page 82 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 83: Gpio

    Figure 32 RTC Battery Circuitry and Serial Schottky Diode 16.6 GPIO Table 24 GPIO Signal Definition COM Express Carrier Type 2 Page 83 of 103 Design Guide...
  • Page 84  GPI signals from a header are shown with protection diodes. The signals are connected for input to the COM Express module.  GPO signals from the COM Express module are shown buffered. The signals are connected to the header with protection diodes. Page 84 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 85: Thermal Signals

    For more detailed information about the thermal management capabilities of the COM Express module, refer to the user's guide of the manufacturer's module. Table 25 Thermal Management Signal Description COM Express Carrier Type 2 Page 85 of 103 Design Guide...

  • Page 86: Power And Reset

    10°C maximum, when making trace- width decisions. Per the IPC charts, external layer traces can carry significantly more current than Page 86 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 87: Reset Signals Definitions

    PWR_OK ; a reset-input signal to the module, SYSRESET# ; various reset outputs from the module including CB_RESET#, PCI_RESET# and IDE_RESET# ; and a PWRBTN# input to the module to allow soft power control. COM Express Carrier Type 2 Page 87 of 103 Design Guide...

  • Page 88: Bios Consideration

    A carrier board Super I/O implementation usually requires BIOS customization to support the Super I/O. If the carrier board uses the same Super I/O as the Emerson-recommended boards, then it may be possible to use the standard legacy BIOS that goes with the particular module. One Super I/O that is supported in the BIOS implementation for the COMX-ATOM-420 is the Winbond W83627THF.

  • Page 89: Mechanical Consideration

    (125 mm x 95 mm) and the extended module (155 mm x 110 mm). Based on customer demand, many COM Express module vendors also offer even smaller form factors with backwards compatibility to the COM Express specification. Figure 34 Mechanical Comparison of Available Com Express Form Factors COM Express Carrier Type 2 Page 89 of 103 Design Guide...

  • Page 90: Heat Spreader

    Usually It is a 3 mm-thick aluminum plate. Figure 35 shows the heat spreader used on the Emerson COMX-ATOM-420. The heat spreader is thermally coupled to the CPU via a thermal gap filler. On some modules, it may also be thermally coupled to other heat generating components with the use of additional thermal gap fillers.

  • Page 91: Layout Guidelines

    GND and PWR planes. This allows layer 4 to be GND referenced. Layer 4 is clear of parts and may be the preferred primary routing layer. 21.1.2 Six-Layer Stack-up Figure 37 Six Layer Stack-Up COM Express Carrier Type 2 Page 91 of 103 Design Guide...

  • Page 92: Eight-Layer Stack-Up

    In a microstrip, a trace or trace pair is referenced to a single ground or power plane. The outer layers of multi-layer PCBs are microstrips. Figure 39 is a diagram of a microstrip cross section Page 92 of 103 COM Express Carrier Type 2 Design Guide...
  • Page 93 There also are quite a few free impedance calculators available on the Web. Most are very basic, but they can be useful. Figure 39 Microstrip Cross Section Figure 40 Stripline Cross Section COM Express Carrier Type 2 Page 93 of 103 Design Guide...

  • Page 94: Routing Rules For High-Speed Differential Interfaces

    21.3 Routing Rules for High-Speed Differential Interfaces The following is a list of suggestions for designing with high-speed differential signals. This should help implement these interfaces while providing maximum COM Express carrier board performance.  Use controlled impedance PCB traces that match the specified differential impedance.
  • Page 95 Figure 41 Layout Considerations In order to determine the necessary trace width, trace height and spacing needed to fulfill the requirements of the interface specification, it's necessary to use an impedance calculator. COM Express Carrier Type 2 Page 95 of 103 Design Guide...

  • Page 96: Pci Express 1.1 Trace Routing Guidelines

    Suggested trace parameters are shown. Using impedance calculation software is recommended to determine trace width, distance to reference planes, and pair spacing applicable to your specific project and PCB materials. Page 96 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 97: Usb Trace Routing Guidelines

    PEG signal lines as short as possible. A maximum of 5 in to the carrier device down and 4 in to a carrier slot is advisable. COM Express Carrier Type 2 Page 97 of 103...

  • Page 98: Sdvo Trace Routing Guidelines

    Suggested trace parameters are shown. Using impedance calculation software is recommended to determine trace width, distance to reference planes, and pair spacing applicable to your specific project and PCB materials. Page 98 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 99: Lan Trace Routing Guidelines

    PCB materials. Also, observe trace geometry definitions and restrictions provided by the device vendor of the PHY. COM Express Carrier Type 2 Page 99 of 103 Design Guide...

  • Page 100: Serial Ata Trace Routing Guidelines

    Suggested trace parameters are shown. Using impedance calculation software is recommended to determine trace width, distance to reference planes, and pair spacing applicable to your specific project and PCB materials. Page 100 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 101: Lvds Trace Routing Guidelines

    The following is a list of suggestions for designing with single-ended signals. This should help implement these interfaces while providing maximum COM Express carrier board performance.  Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices, or ICs that use or generate clocks.

  • Page 102: Pci Trace Routing Guidelines

    Suggested trace parameters are shown. Using impedance calculation software is recommended to determine trace width, distance to reference planes, and pair spacing applicable to your specific project and PCB materials. Page 102 of 103 COM Express Carrier Type 2 Design Guide...

  • Page 103: Ide Trace Routing Guidelines

    PCB materials. 21.4.3 LPC Trace Routing Guidelines Table 36 LPC Trace Routing Guidelines COM Express Carrier Type 2 Page 103 of 103 Design Guide...

Table of Contents