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A
B
8
FROM/TO ASIC
EMIA[2]
7
EMIA[3]
EMIA[4]
EMIA[5]
EMIA[6]
EMIA[7]
EMIA[8]
3.3
EMIA[9]
EMIA[10]
EMIA[11]
0.1
EMIA[12]
CIA[0]
EMIA[13]
NR3001
EMIA[14]
4D02WGJ0470TCE
3.2
EMIA[15]
EMIA[2]
EMIA[16]
EMIA[3]
EMIA[18]
EMIA[4]
0.7
EMIBE0
EMIA[5]
EMILBA
CION
6
0
CPUWAIT
CIA[3]
CIIRQ0
CIIRQ1
0
CIRESET
CIA[4]
EMICS3
NR3002
TS2STRT
4D02WGJ0470TCE
0.7
TS2CLK
EMIA[6]
TS2VAL
EMIA[7]
TS2D[7]
EMIA[8]
1.0
TS2D[6]
EMIA[9]
TS2D[5]
TS2D[4]
0
TS2D[3]
CIA[7]
TS2D[0]
TS2D[1]
0
TS2D[2]
5
FROM/TO FLASH/SDRAM
EMIDM[0]
EMIDM[1]
EMIDM[2]
EMIDM[3]
EMIDM[4]
EMIDM[5]
EMIDM[6]
EMIDM[7]
3.3
EMIOEM
EMIRASM
EMICASM
0
CIA[8]
NR3003
4D02WGJ0470TCE
4
0.8
EMIA[10]
EMIA[11]
FROM/TO OFDM/TUNER
EMIA[12]
0.8
EMIA[13]
FEVALID
FECLK
FED[0]
0.1
CIA[11]
FED[1]
FED[2]
FED[3]
0
CIA[12]
FED[4]
NR3004
FED[5]
4D02WGJ0470TCE
FED[6]
2.4
EMIA[14]
FED[7]
EMIA[15]
FESTROUT
EMIA[16]
0.1
EMIA[18]
0
3
CIREG
0
FROM/TO POWER I/O
GND
P5V
P3V3
2
1
A
B
H-33
C
COMMON INTERFACE SCHEMATIC DIAGRAM
LOGIC IC
LOGIC IC
IC3003
IC3001
SN74LVC373APWR
3.3
CIDDIR
DIR
3.3
NR3005
OE
VCC
4D02WGJ0470TCE
0.3
EMIDM[3]
A1
0
CIA[1]
EMIDM[2]
Q0
Q7
EMIDM[1]
0.3
EMIDM[0]
A2
3.0
D0
D7
0
A3
2.7
D1
D6
0
A4
0
CIA[2]
NR3006
Q1
Q6
4D02WGJ0470TCE
0
EMIDM[7]
A5
0
CIA[5]
EMIDM[6]
Q2
Q5
EMIDM[5]
0
EMIDM[4]
A6
2.5
D2
D5
0
A7
0.5
D3
D4
0
A8
0
CIA[6]
Q3
Q4
0
GND
3.3
GND
LE
C3002
0.1 B
CICE
C3001
0.1 B
LOGIC IC
LOGIC IC
IC3004
IC3002
SN74LVC373APWR
R3002
3.3
3.3
1G
OE
VCC
47
3.3
EMIOEM
0.2
1A1
CIA[9]
Q0
Q7
0.2
2.4
NC
2Y4
D0
D7
R3001
3.3
EMILBA
3.0
1A2
D1
D6
47
0.2
0.3
2Y3
CIA[10]
NC
Q1
Q6
3.3
EMIRASM
0.2
1A3
CIA[13]
Q2
Q5
0.2
0
NC
2Y2
D2
D5
3.2
EMICASM
0.3
1A4
D3
D4
0
0
NC
2Y1
CIA[14]
Q3
Q4
0
3.3
GND
GND
LE
NOTE: THIS SCHEMATIC DIAGRAM IS THE LATEST AT THE TIME
OF PRINTING AND SUBJECT TO CHANGE WITHOUT NOTICE
C
D
E
(DIGITAL PCB)
AND GATE
IC3005
74LVC1G08GV
DH
SN74LVC245APWR
3.3
VCC
3.3
CICE
0E
1
2
3
4
5
0.3
0.3
0
3.3
3.3
0.2
CID[3]
CIIORD
B1
CIOE
CIDDIR
0.2
CID[2]
B2
NOR GATE
IC3006 SN74AHC1G02DCKR
0.3
DH
CID[1]
B3
0.3
CID[0]
B4
0.3
CID[4]
B5
1
2
3
4
5
0.3
CID[5]
0
5.0
0
0
3.3
B6
CPUWAIT
0.2
CID[6]
CIWAIT
B7
OR GATE
0.2
CID[7]
IC3007
74LVC1G32GV
DH
B8
C3003
0.1 B
1
2
3
4
5
5.0
5.0
0
3.3
3.3
C3004
0.1 B
CICD2
CICD1
SN74LVC244APWR
3.3
CIIRQ0
VCC
Q3002
VCC SW
KTA1664-Y-RTF/P
3.3
2G
5.0
5.0
R3007
4.2
0
CIOE
1Y1
10K
0
0
2A4
R3005
5.7
CION
1.2K
0
CIWE
0
1Y2
0
2A3
OR GATE
IC3008
74LVC1G32GV
DH
0
CIIORD
1Y3
0
2A2
0
CIIOWR
1Y4
1
2
3
4
5
0
3.3
3.2
0
3.3
3.3
2A1
R3011
EMICS3
EMIBE0
10K
B3001
P3V3CI
FCM1608CF-600T06
NOTE:THE DC VOLTAGE AT EACH PART WAS MEASURED
WITH THE DIGITAL TESTER WHEN THE COLOR BROADCAST
WAS RECEIVED IN GOOD CONDITION AND PICTURE IS NORMAL.
D
E
F
G
CP3002 30_5027_000_102_000+
PCMCIA CARD EJECTOR
36_5027_068_130_831+
NR3016
GND
4D02WGJ0470TCE
D3
CID[4]
D4
CID[5]
D5
CID[6]
D6
CID[7]
D7
CE1
NR3017
A10
4D02WGJ0470TCE
OE
CIA[10]
A11
CIA[11]
A9
CIA[9]
A8
CIA[8]
A13
A14
NR3018
WE/PGM
4D02WGJ0470TCE
IREQ
CIA[13]
VCC
CIA[14]
NC
VPP1
CIA[12]
MIVAL
NC
NC
MICLK
A12
NR3007
A7
4D02WGJ0470TCE
CIA[7]
A6
A5
CIA[6]
CIA[5]
A4
CIA[4]
A3
A2
NR3008
A1
4D02WGJ0470TCE
A0
CIA[3]
D0
CIA[2]
D1
CIA[1]
D2
CIA[0]
NC
IOCS16
GND
NR3009
GND
4D02WGJ0470TCE
CD1
CID[3]
MOD3
CID[0]
MOD4
CID[1]
MOD5
CID[2]
MOD6
MOD7
NR3010
CE2
4D02WGJ0470TCE
NC
VTGSENS
TS2D[4]
IORD
TS2D[5]
IOWR
TS2D[6]
MISTRT
TS2D[7]
MDI0
MDI1
NR3011
MDI2
4D02WGJ0470TCE
MDI3
FEVALID
VCC
FECLK
NC
VPP2
FESTROUT
MDI4
NC
NC
MDI5
MDI6
MDI7
NR3012
4D02WGJ0470TCE
MOCLK
FED[0]
RESET
FED[1]
WAIT
FED[2]
NC
INP_ACK
FED[3]
REG
MOVAL
MOSTRT
NR3013
MOD0
4D02WGJ0470TCE
MOD1
FED[4]
MOD2
FED[5]
CD2
FED[6]
GND
FED[7]
CI Connecotr
NR3014
4D02WGJ0470TCE
TS2CLK
TS2VAL
TS2STRT
NC
NC
NR3015
4D02WGJ0470TCE
TS2D[3]
TS2D[0]
TS2D[1]
TS2D[2]
CIRESET
CIIRQ1
P5VPCMCIA
PCBDH0
CEF196
F
G
H
8
CP3001
1
2
7
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
6
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
5
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
4
59
60
61
62
63
64
65
66
67
68
3
2
1
H
H-34
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