JVC LT-37DR1BJ Service Manual page 54

MAIN PWB CIRCUIT DIAGRAM (13/13)
AUDIO_RESET
SDA_AUDIO
MAIN PWB(10/13)
SCL_AUDIO
MAIN PWB LCDFRAME
(9/13),(11/13)
EDID_WP
MAIN PWB
HDMI_SEL1
(3/13),(11/13)
HDMI_SEL2
TV_OUT_SW
MAIN PWB
FIL_SW1
(2/13),(11/13)
FIL_SW2
MAIN PWB
RF_AGC
(1/13),(9/13)
CCS
CARIB_RESET
MAIN PWB CDATA_IN
(9/13),(11/13)
CDATA_OUT
CSCLK
CARIB_VD
+------------+---------+---------+---------+---------------------+
| |32DR1|37DR1|42DR1 |DV1 |
|reference |Diff |Diff |Diff |Diff |
+------------+---------+---------+---------+---------------------+
|# R4131 |OPEN |OPEN |OPEN |NRSA63J-101X|
+------------+---------+---------+---------+--------------------- +
|# R4133 |OPEN |OPEN |OPEN |NRSA63J-101X|
+------------+---------+---------+---------+---------------------+
|# R4134 |OPEN |OPEN |OPEN |NRSA63J-101X|
+------------+---------+---------+---------+---------------------+
|# R4137 |OPEN |OPEN |OPEN |NRSA63J-472X|
+------------+---------+---------+---------+---------------------+
|# R4138 |OPEN |OPEN |OPEN |NRSA63J-472X|
+------------+---------+---------+---------+---------------------+
R4150
R4168
3.3V
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
R4107
4.7k
R4101
33
76
77 NC
78 NC
R4161 OPEN
79 NC
R4162 OPEN
80 NC
R4163 OPEN
81 NC
R4164 OPEN
82 NC
R4165 OPEN
83 NC
R4166 OPEN
84 NC
R4167 OPEN
85 NC
86 NC
87 NC
88 NC
R4108
89 NC
OPEN
90 NC
TP4109
91 NC
TP4110
92 NC
R4102
OPEN
93 RF_AGC
94 AVSS
R4103 100 R4109
95 EE_SENS
OPEN
C4132 OPEN
96 VREF
C4101 0.1
97 AVCC
R4104 100
98 MISO
R4105 100
99 MOSI
R4106 100 R4110
SCLK
100
3.3k
R4111 4.7k
R4112 4.7k
1 2 3 4 5 6 7 8
TP4101
B1
TP4102
C4113
10
TP4103
TP4104
R4113
4.7k
R4116
100
D_GND
R4173
MAIN PWB ASS'Y(13/13)
SFY-1008A-H3
(No.YA688<Rev.001>)2-31
100
100
R4147
10k
R4146
10k
R4148
10k
R4143 4.7k
CARIB_RST 50
CS 49
*R4137
NC 48
*R4138
NC 47
SCL_FORZA 46
SDA_FORZA 45
E8_CE 44
FORZA_RST 43
R4139 4.7k
NC 42
R4140 OPEN
NC 41
R4136
3.3k
NC 40
E8_EPM 39
IC4101 R4135
3.3k
NC 38
MODE_SEL 37
AV PROCESS R4155 4.7k
NC 36
CPU
R4156 4.7k
NC 35
T2R_RXD 34
T2R_TXD 33
E8_BUSY 32
E8_CLK 31
E8_DATAI 30
E8_DATAO 29
SDA3 28
SCL3 27
4.7k
R4157
NC 26
4.7k
R4158
R4159 4.7k
4.7k
R4160
TP4106
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TP4105
3 2 1
X4101 12.5MHz
NAX0552-001X
1k
IC4103
TC74VHC74FT-X
1CLR
1D
1CK
R4188 1PR
0
1Q
1Q
GND
2-32(No.YA688<Rev.001>)
LCD_POW_1
BL_ON
3.3V
CN4101
QGA1501F4-10W
1 3.3V
2 GND
E8_CE
3 E8_WR
E8_EPM
4 E8_HOLD
E8_CS
5 E8_CS
E8_CLK
6 E8_CLK
E8_DATAI
7 E8_DATAI
E8_DATAO
8 E8_DATAO
E8_RESET
9 E8_RESET
CNVSS
10 CNVSS
D_GND
*R4134
FORZA_SCL
*R4133
FORZA_SDA
100
R4132 E8_CE
*R4131
100
R4130 E8_EPM
R4129 OPEN
LCD_POW_IN
JIG
100
R4128
PC_TO_CARIB
R4127 100
CARIB_TO_PC
R4126 100 E8_CS
REQ
100
R4125 E8_CLK
BL_ON_IN
R4124 100 E8_DATAI
EE_SENSE
R4123 100 E8_DATAO
0
R4122
SDA3
R4121 0
SCL3
M_RST
RGB_VSYNC
M16_DIM
IC4102
M24C32-WMN6-X
SETTING MEMORY
R4192
R4193
3.3V
VCC
2CLR
2D
2CK
OPEN
R4189
2PR
2Q
2Q
C4131
0.01
MAIN PWB(8/13)
LVDS_SEL
MAIN PWB(9/13),(12/13)
MAIN PWB(9/13)
BL_STATUS
OPEN
E8/E8a Emulator
MAIN PWB(8/13)
FORZA_RESET
MAIN PWB(11/13)
MAIN PWB(1/13),(9/13),(11/13)
MAIN PWB(9/13)
MAIN PWB(7/13),(9/13)
MAIN PWB(9/13)
3.3V
IC4104
OPEN
OE1 VCC
OPEN
A1 OE2 BM_I2C_SW
R4190 OPEN
OPEN
B2 B1
R4195 OPEN
GND A2
MAIN PWB(11/13)
D_GND
c10611001a013_0204_13/13_0.1